OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

An abstraction library for interfacing EDA tools

draws an SVG schematic from a JSON netlist

SystemVerilog to Verilog conversion

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

A VHDL frontend for Yosys

FPGA tool performance profiling

A Python package to use FPGA development tools programmatically.

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

XCrypto: a cryptographic ISE for RISC-V

Examples for the Lushay Labs tang nano 9k series

Physical Design Flow from RTL to GDS using Opensource tools.

Arduino compatible – Cortex M4F & FPGA Development Board

Plugins for Yosys developed as part of the F4PGA project.

RealtimeIO for LinuxCNC based on an FPGA

sliding DFT for FPGA, targetting Lattice ICE40 1k