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Test 0 to stress out m-mode / u-mode transitions
FRISCV #232: Commit 3662671 pushed by dpretet
September 17, 2023 14:48 28m 51s privilege
September 17, 2023 14:48 28m 51s
Test 0 to stress out m-mode / u-mode transitions
FRISCV #231: Commit 062d8f7 pushed by dpretet
September 17, 2023 14:43 4m 50s privilege
September 17, 2023 14:43 4m 50s
Test 0 to stress out m-mode / u-mode transitions
FRISCV #230: Commit b8a1913 pushed by dpretet
September 17, 2023 13:59 29m 45s privilege
September 17, 2023 13:59 29m 45s
Update README files
FRISCV #229: Commit dbe1096 pushed by dpretet
September 16, 2023 11:53 27m 57s privilege
September 16, 2023 11:53 27m 57s
Update README files
FRISCV #228: Commit 747b783 pushed by dpretet
September 16, 2023 10:02 30m 8s privilege
September 16, 2023 10:02 30m 8s
Update documentation
FRISCV #227: Commit 308a116 pushed by dpretet
September 14, 2023 19:50 53m 45s privilege
September 14, 2023 19:50 53m 45s
Update documentation
FRISCV #226: Commit f4b1d62 pushed by dpretet
September 14, 2023 19:49 34m 13s privilege
September 14, 2023 19:49 34m 13s
Update documentation
FRISCV #225: Commit bd6ce0f pushed by dpretet
September 14, 2023 19:45 30m 11s privilege
September 14, 2023 19:45 30m 11s
Add priv_sec testsuite in github actions
FRISCV #224: Commit fee2e0e pushed by dpretet
September 13, 2023 18:48 32m 44s privilege
September 13, 2023 18:48 32m 44s
New: Put in place configuration files for testbenchs
FRISCV #223: Commit 939c0bd pushed by dpretet
September 13, 2023 18:35 13m 16s privilege
September 13, 2023 18:35 13m 16s
New: Put in place configuration files for testbenchs
FRISCV #222: Commit a9cd8fb pushed by dpretet
September 13, 2023 18:28 20m 28s privilege
September 13, 2023 18:28 20m 28s
New: Implement U-mode RTL
FRISCV #221: Commit 217290d pushed by dpretet
September 12, 2023 11:32 29m 37s privilege
September 12, 2023 11:32 29m 37s
New: Implement U-mode RTL
FRISCV #220: Commit c44ca5a pushed by dpretet
September 11, 2023 19:28 26m 36s privilege
September 11, 2023 19:28 26m 36s
New: Implement U-mode RTL
FRISCV #219: Commit 2c96739 pushed by dpretet
September 10, 2023 16:54 29m 5s privilege
September 10, 2023 16:54 29m 5s
New: Implement U-mode RTL
FRISCV #218: Commit efb73ca pushed by dpretet
September 10, 2023 16:52 6m 30s privilege
September 10, 2023 16:52 6m 30s
New: Put in place SUPERVISOR, HYPERVISOR and USER mode enable parameters
FRISCV #217: Commit 90cc3e1 pushed by dpretet
September 10, 2023 07:29 27m 10s privilege
September 10, 2023 07:29 27m 10s
September 9, 2023 19:19 4m 4s
Start priviledge mode support
FRISCV #215: Commit 472246b pushed by dpretet
September 8, 2023 14:34 31m 34s priviledge
September 8, 2023 14:34 31m 34s
New: JAL execution doesn't wait for anymore processing ready
FRISCV #214: Commit 75b43ac pushed by dpretet
September 8, 2023 11:56 45m 35s v1.5.1
September 8, 2023 11:56 45m 35s
New: JAL execution doesn't wait for anymore processing ready
FRISCV #213: Commit 75b43ac pushed by dpretet
September 8, 2023 11:56 28m 0s master
September 8, 2023 11:56 28m 0s
Update SystemVerilog README
FRISCV #212: Commit d0c9856 pushed by dpretet
September 6, 2023 13:47 31m 52s master
September 6, 2023 13:47 31m 52s
New: io / param describes internal parameters, not exposed in top level
FRISCV #211: Commit 20b39fa pushed by dpretet
September 6, 2023 12:13 27m 55s master
September 6, 2023 12:13 27m 55s
Change: Update README files
FRISCV #210: Commit e4203d6 pushed by dpretet
September 6, 2023 07:44 30m 20s master
September 6, 2023 07:44 30m 20s
typo fix in io parameters chapter
FRISCV #209: Commit fa88568 pushed by dpretet
September 6, 2023 07:14 29m 27s master
September 6, 2023 07:14 29m 27s
Change: An execution prints the list of testcase status, not just a
FRISCV #208: Commit 988b7ed pushed by dpretet
September 6, 2023 06:58 31m 5s master
September 6, 2023 06:58 31m 5s