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New: Put in place configuration files for testbenchs
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@dpretet
dpretet committed Sep 13, 2023
1 parent 217290d commit a9cd8fb
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3 changes: 2 additions & 1 deletion doc/project_mgt_hw.md
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Original file line number Diff line number Diff line change
Expand Up @@ -135,7 +135,6 @@ Verification/Validation
- [ ] https://github.com/chipsalliance/Surelog
- [ ] https://stackoverflow.com/questions/65534532/how-to-estimation-a-chip-size-with-standard-cell-library
- [ ] Core config
- [ ] Supporter des set de config du core en test bench.
- [ ] Faire un test de synthèse selon les configs du core
- [ ] Support cache disable in testbench
- [ ] Error Logger Interface
Expand Down Expand Up @@ -173,6 +172,8 @@ Hardware Tests

# DONE

- [X] v1.6.0
- [X] Supporter des set de config du core en test bench.
- [X] v1.5.1: maintenance
- [X] Preload jal even if processing is busy
- [X] Print des tests qui ne marchent pas, un par un, dans le bash
Expand Down
34 changes: 18 additions & 16 deletions rtl/friscv_control.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -257,8 +257,10 @@ module friscv_control
else if (cause=='h0) get_mcause_desc = "Instruction address misaligned";
else if (cause=='h4) get_mcause_desc = "LOAD address misaligned";
else if (cause=='h6) get_mcause_desc = "STORE address misaligned";
else if (cause=='h2) get_mcause_desc = "Instruction decoding error";
else if (cause=='hB) get_mcause_desc = "Environment call";
else if (cause=='h10) get_mcause_desc = "Instruction decoding error";
else if (cause=='h8) get_mcause_desc = "Environment call (U-mode)";
else if (cause=='hB) get_mcause_desc = "Environment call (M-mode)";
else if (cause=='h2) get_mcause_desc = "Illegal instruction";
// Asynchronous Trap
else if (cause=='h80000003) get_mcause_desc = "Machine Software Interrupt";
else if (cause=='h80000007) get_mcause_desc = "Machine Timer Interrupt";
Expand Down Expand Up @@ -1094,7 +1096,7 @@ module friscv_control
(sys[`IS_MRET]) ? inst_ready :
(sys[`IS_CSR] && csr[9:8] != 2'b00) ? inst_ready :
// Check if WFI must be trapped or not
(sys[`IS_WFI] ) ? inst_ready :
// (sys[`IS_WFI] ) ? inst_ready :
'0;
end else begin : NO_UMODE
assign illegal_instruction = '0;
Expand Down Expand Up @@ -1164,26 +1166,27 @@ module friscv_control
(csr_sb[`MTIP]) ? {1'b1, {XLEN-5{1'b0}}, 4'h7} :
(csr_sb[`MEIP]) ? {1'b1, {XLEN-5{1'b0}}, 4'hB} :
// then follow sync exceptions
(illegal_instruction) ? {{XLEN-4{1'b0}}, 4'h2} :
(csr_ro_wr) ? {{XLEN-4{1'b0}}, 4'h2} :
(inst_dec_error) ? {{XLEN-4{1'b0}}, 4'h2} :
(inst_addr_misaligned) ? {XLEN{1'b0}} :
(ecall_umode) ? {{XLEN-4{1'b0}}, 4'h8} :
(ecall_mmode) ? {{XLEN-4{1'b0}}, 4'hB} :
(sys[`IS_EBREAK]) ? {{XLEN-4{1'b0}}, 4'h3} :
(store_misaligned) ? {{XLEN-4{1'b0}}, 4'h6} :
(load_misaligned) ? {{XLEN-4{1'b0}}, 4'h4} :
{XLEN{1'b0}};
(illegal_instruction) ? {{XLEN-4{1'b0}}, 4'h2} :
(csr_ro_wr) ? {{XLEN-4{1'b0}}, 4'h2} :
(inst_addr_misaligned) ? '0 :
(ecall_umode) ? {{XLEN-4{1'b0}}, 4'h8} :
(ecall_mmode) ? {{XLEN-4{1'b0}}, 4'hB} :
(sys[`IS_EBREAK]) ? {{XLEN-4{1'b0}}, 4'h3} :
(store_misaligned) ? {{XLEN-4{1'b0}}, 4'h6} :
(load_misaligned) ? {{XLEN-4{1'b0}}, 4'h4} :
(inst_dec_error) ? {{XLEN-5{1'b0}}, 5'h18} :
'0;

// MTVAL: exception-specific information
assign mtval_info = (inst_dec_error) ? instruction :
(wfi_not_allowed) ? instruction :
(illegal_instruction) ? instruction :
(inst_dec_error) ? instruction :
(csr_ro_wr) ? instruction :
(inst_addr_misaligned) ? pc_reg :
(sys[`IS_ECALL]) ? pc_reg :
(sys[`IS_EBREAK]) ? pc_reg :
{XLEN{1'b0}};
'0;

// Trigger the trap handling execution in main FSM

Expand All @@ -1194,8 +1197,7 @@ module friscv_control
assign sync_trap_occuring = csr_ro_wr |
inst_addr_misaligned |
load_misaligned |
// wfi_not_allowed |
// illegal_instruction |
illegal_instruction |
store_misaligned |
inst_dec_error ;

Expand Down
144 changes: 112 additions & 32 deletions rtl/friscv_registers.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -76,12 +76,63 @@ module friscv_registers
input wire [XLEN -1:0] csr_rd_val
);

//------------------------------------------------
// Function to print register name and information
// @i: register number to get info
// @returns a string describing the register
//------------------------------------------------
function string get_name(integer i);
get_name = "!?";
if (i== 0) get_name = " zero (hardwired zero)";
if (i== 1) get_name = " ra (return address)";
if (i== 2) get_name = " sp (stack pointer)";
if (i== 3) get_name = " gp (global pointer)";
if (i== 4) get_name = " tp (thread pointer)";
if (i== 5) get_name = " t0 (temporary register 0)";
if (i== 6) get_name = " t1 (temporary register 0)";
if (i== 7) get_name = " t2 (temporary register 0)";
if (i== 8) get_name = " s0_fp (saved register 0 / frame pointer)";
if (i== 9) get_name = " s1 (saved register 1)";
if (i==10) get_name = " a0 (function argument 0 / return value 0)";
if (i==11) get_name = " a1 (function argument 1 / return value 1)";
if (i==12) get_name = " a2 (function argument 2)";
if (i==13) get_name = " a3 (function argument 3)";
if (i==14) get_name = " a4 (function argument 4)";
if (i==15) get_name = " a5 (function argument 5)";
if (i==16) get_name = " a6 (function argument 6)";
if (i==17) get_name = " a7 (function argument 7)";
if (i==18) get_name = " s2 (saved register 2)";
if (i==19) get_name = " s3 (saved register 3)";
if (i==20) get_name = " s4 (saved register 4)";
if (i==21) get_name = " s5 (saved register 5)";
if (i==22) get_name = " s6 (saved register 6)";
if (i==23) get_name = " s7 (saved register 7)";
if (i==24) get_name = " s8 (saved register 8)";
if (i==25) get_name = " s9 (saved register 9)";
if (i==26) get_name = " s10 (saved register 10)";
if (i==27) get_name = " s11 (saved register 11)";
if (i==28) get_name = " t3 (temporary register 3)";
if (i==29) get_name = " t4 (temporary register 4)";
if (i==30) get_name = " t5 (temporary register 5)";
if (i==31) get_name = " t6 (temporary register 6)";
endfunction


// E extension limiting the register number to 16
localparam REGNUM = (RV32E) ? 16 : 32;

// ISA registers 0-31
logic [XLEN-1:0] regs [REGNUM-1:0];

// Tracer setup
`ifdef TRACE_REGISTERS
integer f;
string fname;
initial begin
$sformat(fname, "trace_%s.txt", "registers");
f = $fopen(fname, "w");
end
`endif

generate

Expand Down Expand Up @@ -120,7 +171,7 @@ module friscv_registers
end else if (csr_rd_wr && csr_rd_addr==i) begin
regs[i] = csr_rd_val;

// Access from data memory controller
// Access from processing units
end else if (|proc_rd_wr) begin
for (u=0;u<NB_ALU_UNIT;u=u+1) begin
if (proc_rd_wr[u] && proc_rd_addr[u*5+:5]==i) begin
Expand All @@ -135,9 +186,37 @@ module friscv_registers
end
end

`ifdef TRACE_REGISTERS
always @ (posedge aclk) begin
if (aresetn) begin

if (ctrl_rd_wr && ctrl_rd_addr==i)
$fwrite(f, "(@ %0t) Ctrl Write : reg[%2d] = 0x%x (0xf) %s\n", $realtime, i, ctrl_rd_val, get_name(i));

if (csr_rd_wr && csr_rd_addr==i)
$fwrite(f, "(@ %0t) CSR Write : reg[%2d] = 0x%x (0xf) %s\n", $realtime, i, csr_rd_val, get_name(i));

for (u=0;u<NB_ALU_UNIT;u=u+1) begin
if (proc_rd_wr[u] && proc_rd_addr[u*5+:5]==i) begin

if (u==0)
$fwrite(f, "(@ %0t) ALU Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
else if (u==1)
$fwrite(f, "(@ %0t) Memfy Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
else if (u==2)
$fwrite(f, "(@ %0t) M_Ext Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
else
$fwrite(f, "(@ %0t) Ext%d Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, u, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));

end
end
end
end
`endif
end
endgenerate


generate

if (SYNC_READ==0) begin: COMB_READ
Expand Down Expand Up @@ -184,37 +263,38 @@ module friscv_registers
end
endgenerate

assign x1_ra = regs[1];
assign x2_sp = regs[2];
assign x3_gp = regs[3];
assign x4_tp = regs[4];
assign x5_t0 = regs[5];
assign x6_t1 = regs[6];
assign x7_t2 = regs[7];
assign x8_s0_fp = regs[8];
assign x9_s1 = regs[9];
assign x10_a0 = regs[10];
assign x11_a1 = regs[11];
assign x12_a2 = regs[12];
assign x13_a3 = regs[13];
assign x14_a4 = regs[14];
assign x15_a5 = regs[15];
assign x16_a6 = regs[16];
assign x17_a7 = regs[17];
assign x18_s2 = regs[18];
assign x19_s3 = regs[19];
assign x20_s4 = regs[20];
assign x21_s5 = regs[21];
assign x22_s6 = regs[22];
assign x23_s7 = regs[23];
assign x24_s8 = regs[24];
assign x25_s9 = regs[25];
assign x26_s10 = regs[26];
assign x27_s11 = regs[27];
assign x28_t3 = regs[28];
assign x29_t4 = regs[29];
assign x30_t5 = regs[30];
assign x31_t6 = regs[31];
// Debug purpose only
assign x1_ra = regs[1];
assign x2_sp = regs[2];
assign x3_gp = regs[3];
assign x4_tp = regs[4];
assign x5_t0 = regs[5];
assign x6_t1 = regs[6];
assign x7_t2 = regs[7];
assign x8_s0_fp = regs[8];
assign x9_s1 = regs[9];
assign x10_a0 = regs[10];
assign x11_a1 = regs[11];
assign x12_a2 = regs[12];
assign x13_a3 = regs[13];
assign x14_a4 = regs[14];
assign x15_a5 = regs[15];
assign x16_a6 = regs[16];
assign x17_a7 = regs[17];
assign x18_s2 = regs[18];
assign x19_s3 = regs[19];
assign x20_s4 = regs[20];
assign x21_s5 = regs[21];
assign x22_s6 = regs[22];
assign x23_s7 = regs[23];
assign x24_s8 = regs[24];
assign x25_s9 = regs[25];
assign x26_s10 = regs[26];
assign x27_s11 = regs[27];
assign x28_t3 = regs[28];
assign x29_t4 = regs[29];
assign x30_t5 = regs[30];
assign x31_t6 = regs[31];

endmodule

Expand Down
6 changes: 6 additions & 0 deletions test/c_testsuite/config.cfg
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Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
XLEN,32
CACHE_EN,1
CACHE_BLOCK_W,128
GEN_EIRQ,0
ERROR_STATUS_X31,1
USER_MODE,0
18 changes: 6 additions & 12 deletions test/c_testsuite/run.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -11,12 +11,12 @@
# Variables and setup
#------------------------------------------------------------------------------

cfg_file="config.cfg"

# Timeout upon which the simulation is ran
TIMEOUT=200000
# Minumum value the program counter should reach in bytes
MIN_PC=65692
# Check X31 used to detect testcase execution error
ERROR_STATUS_X31=1

source ../common/functions.sh

Expand All @@ -35,18 +35,17 @@ main() {

# Clean up compiled applications and exit
if [ $do_clean -eq 1 ]; then
clean
for dir in tests/*/; do
if [ "$dir" != "tests/common/" ]; then
echo "INFO: Clean $dir"
make clean -C "$dir";
fi
done
exit 0;
clean
fi

# Build all applications
if [ $NO_COMPILE -eq 0 ]; then
if [ "$NO_COMPILE" -eq 0 ]; then
echo "INFO: C tests"
set -e
for dir in tests/*/; do
Expand All @@ -60,17 +59,12 @@ main() {

# If user specified a testcase, or a testsuite, use it
if [[ -n $TC ]]; then
run_testsuite "$TC"
run_testsuite "$TC" "$cfg_file"
# Else run all the supported testsuite
else
# Execute the testsuites
run_testsuite "./tests/*.v"
run_testsuite "./tests/*.v" "$cfg_file"
fi

# OK, sounds good, exit gently
echo -e "${GREEN}SUCCESS: C testsuite successfully terminated ^^${NC}"

exit 0
}

main "$@"
6 changes: 5 additions & 1 deletion test/common/friscv_testbench.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,10 @@ module friscv_testbench(
`define TB_CHOICE 0
`endif

`ifndef USER_MODE
`define USER_MODE 0
`endif

parameter TB_CHOICE = (`TB_CHOICE==0) ? "CORE" : "PLATFORM";

// Instruction length
Expand All @@ -102,7 +106,7 @@ module friscv_testbench(
// Support supervisor mode
parameter SUPERVISOR_MODE = 0;
// Support user mode
parameter USER_MODE = 1;
parameter USER_MODE = `USER_MODE;
// Insert a pipeline on instruction bus coming from the controller
parameter PROCESSING_BUS_PIPELINE = 1;

Expand Down
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