Skip to content

Commit

Permalink
New: JAL execution doesn't wait for anymore processing ready
Browse files Browse the repository at this point in the history 
     CPI = 2.03
  • Loading branch information
@dpretet
dpretet committed Sep 8, 2023
1 parent d0c9856 commit 75b43ac
Show file tree
Hide file tree
Showing 5 changed files with 88 additions and 36 deletions.
34 changes: 34 additions & 0 deletions doc/perf_benchmark.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -315,3 +315,37 @@ Algorithms:
- Printf execution: 51919 cycles
- Xoshiro128++ execution: 241840 cycles
- Pool Arena execution: 1675539 cycles

# 230908: 1.5.1

JAL doesn't wait for anymore processing to be ready

General statistics:
- Start time: 6493
- End time: 1999898
- Total elapsed time: 1993405 cycles
- Instret start: 2174
- Instret end: 982920
- Retired instructions: 980746

Instruction Bus Request:
- active cycles: 1908226
- sleep cycles: 0
- stall cycles: 85181

Inst Bus Completion:
- active cycles: 1102166
- sleep cycles: 128389
- stall cycles: 762521

Processing Bus:
- active cycles: 815637
- sleep cycles: 815252
- stall cycles: 335831

Algorithms:
- Chacha20 execution: 55154 cycles
- Matrix execution: 10596 cycles
- Printf execution: 49904 cycles
- Xoshiro128++ execution: 236723 cycles
- Pool Arena execution: 1640273 cycles
2 changes: 1 addition & 1 deletion doc/project_mgt_hw.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,6 @@ AXI4 Infrastructure

Control

- [ ] Preload jal even if processing is busy
- [ ] Detect IO requests to forward info for FENCE execution
- [ ] Move LUI into processing to prepare future extension support
- [ ] Read ASM to be sure its used for processing and not control
Expand Down Expand Up @@ -172,6 +171,7 @@ Hardware Tests
# DONE

- [X] v1.5.1: maintenance
- [X] Preload jal even if processing is busy
- [X] Print des tests qui ne marchent pas, un par un, dans le bash
- [X] Join errors after a test status
- [X] Review readme files
Expand Down
74 changes: 47 additions & 27 deletions rtl/friscv_control.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -134,13 +134,13 @@ module friscv_control

// Control fsm
typedef enum logic[3:0] {
BOOT = 0,
FETCH = 1,
RELOAD = 2,
FENCE = 3,
BOOT = 0,
FETCH = 1,
RELOAD = 2,
FENCE = 3,
FENCE_I = 4,
WFI = 5,
EBREAK = 6
WFI = 5,
EBREAK = 6
} pc_fsm;

pc_fsm cfsm;
Expand Down Expand Up @@ -256,7 +256,7 @@ module friscv_control
else if (cause=='h80000007) get_mcause_desc = "Machine Timer Interrupt";
else if (cause=='h8000000B) get_mcause_desc = "Machine External Interrupt";
// All other unknown interrupts
else get_mcause_desc = "Unkown Trap Cause";
else get_mcause_desc = "Unknown Trap Cause";
endfunction
`endif

Expand Down Expand Up @@ -298,9 +298,9 @@ module friscv_control
// CSR Shared bus extraction
///////////////////////////////////////////////////////////////////////////

assign sb_mtvec = csr_sb[`MTVEC+:XLEN];
assign sb_mstatus = csr_sb[`MSTATUS+:XLEN];
assign sb_mepc = csr_sb[`MEPC+:XLEN];
assign sb_mtvec = csr_sb[`MTVEC +: XLEN];
assign sb_mstatus = csr_sb[`MSTATUS +: XLEN];
assign sb_mepc = csr_sb[`MEPC +: XLEN];

assign push_inst = rvalid & (arid == rid);

Expand All @@ -310,7 +310,7 @@ module friscv_control
// This FIFO is controlled by the FSM issuing read request and can be
// flushed in case branching or jumping is required.
///////////////////////////////////////////////////////////////////////////
if (OSTDREQ_NUM > 0) begin
if (OSTDREQ_NUM > 0) begin: INST_FIFO

assign rready = !fifo_full;

Expand Down Expand Up @@ -341,7 +341,7 @@ module friscv_control
///////////////////////////////////////////////////////////////////////////
// No input FIFO, the read data channel feeds directly the controller
///////////////////////////////////////////////////////////////////////////
end else begin
end else begin : INST_PATH

assign instruction = rdata;
assign inst_ready = push_inst;
Expand Down Expand Up @@ -590,21 +590,31 @@ module friscv_control
///////////////////////////////////////////////////////////

//
// - ECALL / RET / JAL / JALR / Branches
// - ECALL / MRET / JALR / Any branching
//
if (inst_ready && !proc_busy &&
(jump_branch || sys[`IS_ECALL] || sys[`IS_MRET] || trap_occuring))
begin

// Get a new ID for the new batch
arid <= next_id(arid, MAX_ID, AXI_ID_MASK);

// ECALL / Trap handling
if (sys[`IS_ECALL] || trap_occuring) araddr <= mtvec;
// MRET
else if (sys[`IS_MRET]) araddr <= sb_mepc;
// Any jump / branch
// jalr / branch
else araddr <= pc;

//
// JAL
//
end else if (inst_ready && jal) begin

// Get a new ID for the new batch
arid <= next_id(arid, MAX_ID, AXI_ID_MASK);
araddr <= pc;

//
// - FENCE.i execution
//
Expand Down Expand Up @@ -648,7 +658,7 @@ module friscv_control

// Needs to jump or branch thus stop the pipeline
// and reload new instructions
end else if (jal | jalr | branching) begin
end else if (jalr | branching) begin

if (!cant_jump) begin
print_instruction;
Expand All @@ -657,15 +667,25 @@ module friscv_control

if (jump_branch && !cant_jump) begin
`ifdef USE_SVL
if (jal | jalr) log.info("Jumping");
else log.info("Branching");
if (jalr) log.info("JALR");
else log.info("Branching");
`endif
end

if (jump_branch && !cant_jump) begin
flush_pipe <= 1'b1;
end

end else if (jal) begin

`ifdef USE_SVL
log.info("JAL");
`endif

print_instruction;
pc_reg <= pc;
flush_pipe <= 1'b1;

// Any sys instruction:
// - ECALL (0) / EBREAK (1) / CSR (2) / MRET (3) / SRET (4) / WFI (5)
end else if (|sys || |fence) begin
Expand Down Expand Up @@ -746,7 +766,7 @@ module friscv_control
// All other instructions
end else if (processing) begin

if (~cant_process) begin
if (!cant_process) begin
print_instruction;
flush_pipe <= 1'b0;
pc_reg <= pc;
Expand Down Expand Up @@ -863,7 +883,7 @@ module friscv_control
end else if (|sys || |fence) begin

// Reach an ECALL instruction, jump to trap handler
if (sys[`IS_ECALL] && ~proc_busy && csr_ready) begin
if (sys[`IS_ECALL] && !proc_busy && csr_ready) begin

mepc_wr <= 1'b1;
mepc <= pc_reg;
Expand All @@ -879,13 +899,13 @@ module friscv_control
mcause <= mcause_code;

// Reach a MRET instruction, jump to exception return
end else if (sys[`IS_MRET] && ~proc_busy && csr_ready) begin
end else if (sys[`IS_MRET] && !proc_busy && csr_ready) begin

mstatus_wr <= 1'b1;
mstatus <= mstatus_for_mret;

// Reach an WFI, wait for an interrupt
end else if (sys[`IS_WFI] && ~proc_busy && csr_ready) begin
end else if (sys[`IS_WFI] && !proc_busy && csr_ready) begin

mepc_wr <= 1'b1;
mepc <= pc_plus4;
Expand Down Expand Up @@ -921,12 +941,12 @@ module friscv_control
assign arprot = 3'b100;

// Needs to jump or branch, the request to cache/RAM needs to be restarted
assign jump_branch = (branching & goto_branch) | jal | jalr;
assign jump_branch = (branching & goto_branch) | jalr;

// LUI and AUIPC are executed internally, not in processing
assign lui_auipc = lui | auipc;

assign cant_jump = (jal | jalr | branching) && (proc_busy | !csr_ready);
assign cant_jump = (jalr | branching) && (proc_busy | !csr_ready);

assign cant_process = processing & (!proc_ready | !csr_ready);

Expand Down Expand Up @@ -1136,11 +1156,11 @@ module friscv_control
csr_sb[`MTIP] |
csr_sb[`MEIP] ;

assign sync_trap_occuring = csr_ro_wr |
assign sync_trap_occuring = csr_ro_wr |
inst_addr_misaligned |
load_misaligned |
store_misaligned |
inst_dec_error;
load_misaligned |
store_misaligned |
inst_dec_error ;

assign trap_occuring = async_trap_occuring | sync_trap_occuring;

Expand Down
7 changes: 3 additions & 4 deletions test/c_testsuite/tests/functions.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,7 @@ EF F0 5F FA 93 07 05 00 B3 87 F4 00 13 85 07 00
67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
93 8F 1F 00 13 00 00 00 03 24 C1 00 13 01 01 01
67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
97 07 07 00 93 87 07 D9 03 A7 07 00 93 07 10 00
63 1A F7 00 97 07 07 00 93 87 C7 D7 23 A0 07 00
6F 00 40 01 97 07 07 00 93 87 C7 D6 13 07 10 00
23 A0 E7 00 97 07 07 00 93 87 C7 D5 83 A7 07 00
B7 07 08 00 03 A7 07 00 93 07 10 00 63 18 F7 00
B7 07 08 00 23 A0 07 00 6F 00 00 01 B7 07 08 00
13 07 10 00 23 A0 E7 00 B7 07 08 00 83 A7 07 00
13 85 07 00 03 24 C1 00 13 01 01 01 67 80 00 00
7 changes: 3 additions & 4 deletions test/c_testsuite/tests/functions/functions.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,7 @@ EF F0 5F FA 93 07 05 00 B3 87 F4 00 13 85 07 00
67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
93 8F 1F 00 13 00 00 00 03 24 C1 00 13 01 01 01
67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
97 07 07 00 93 87 07 D9 03 A7 07 00 93 07 10 00
63 1A F7 00 97 07 07 00 93 87 C7 D7 23 A0 07 00
6F 00 40 01 97 07 07 00 93 87 C7 D6 13 07 10 00
23 A0 E7 00 97 07 07 00 93 87 C7 D5 83 A7 07 00
B7 07 08 00 03 A7 07 00 93 07 10 00 63 18 F7 00
B7 07 08 00 23 A0 07 00 6F 00 00 01 B7 07 08 00
13 07 10 00 23 A0 E7 00 B7 07 08 00 83 A7 07 00
13 85 07 00 03 24 C1 00 13 01 01 01 67 80 00 00

0 comments on commit 75b43ac

Please sign in to comment.