Add VexRiscv CPU; Use system structure similar to iob_soc_opencryptolinux. #945
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Structure similar to iob_soc_opencryptolinux system.
WIP: Simulation is stuck before boot. Likely due to wrong address ranges. There are also a lot of warnings about AXI_ADDR_W of signals. This is because interconnect expects 24 bits (configurable via AXI_ADDR_W parameter) and the peripherals/cpu dont use the same width.
different address widths.
WIP: CPU reads first prebootloader instruction and gets stuck. Likely because ROM does not yet support burst transfers.
Rename software sources to use underscores; Re-add csrs to bootrom. Allows csrs generator to handle AXI to iob conversion. TODO: Update py2hwsw to fix AXI interface of generated csrs.
Update py2hwsw version. Pre-Bootloader seems to run, but not bootloader. Seems to keep resetting back to pre-bootloader.
- Fix prebootloader copy size. - Fix interconnect wrapper for single master. - Fix iob-soc scripts. - Fix rdata timing bug in axi2iob module. - Update vexriscv submodule.
IOb-SoC no longer uses iob-cache.
Update py2hwsw.
This was referenced Sep 10, 2024
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Replace PicoRV32 CPU by VexRiscv.
Remove iob_cache (use one included in VexRiscv).
Replace system iob_splits by single axi_interconnect.