IObundle · jjts · Sep 10, 2024 · Sep 3, 2024 · Sep 4, 2024 · Sep 6, 2024
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -99,22 +99,6 @@ jobs:
       - name: run LIB test
         run: nix-shell --run "make -C lib sim-test"
 
-  cache:
-    runs-on: self-hosted
-    timeout-minutes: 20
-    if: ${{ !cancelled() }}
-    needs: [ cyclonev ]
-
-    steps:
-      - uses: actions/checkout@v4
-        with:
-          submodules: 'recursive'
-      - name: Clean untracked files and directories (like old submodules)
-        run: git clean -ffdx
-      - name: run simulation test
-        run: make -C submodules/CACHE sim-test
-      - name: run fpga test
-        run: make -C submodules/CACHE fpga-test
   doc:
     runs-on: self-hosted
     timeout-minutes: 60

diff --git a/.gitmodules b/.gitmodules
@@ -1,3 +1,3 @@
-[submodule "submodules/CACHE"]
-	path = submodules/CACHE
-	url = [email protected]:IObundle/iob-cache.git
+[submodule "submodules/VEXRISCV"]
+	path = submodules/VEXRISCV
+	url = [email protected]:IObundle/iob-vexriscv.git
diff --git a/document/tsrc/presentation.tex b/document/tsrc/presentation.tex
@@ -134,10 +134,10 @@
     \begin{lstlisting}
 #include "system.h"
 #include "periphs.h"
-#include "iob-uart.h"
+#include "iob_uart.h"
 #include "printf.h"
 
-#include "iob-timer.h"
+#include "iob_timer.h"
 
 int main()
 {

diff --git a/hardware/fpga/fpga_build.mk b/hardware/fpga/fpga_build.mk
@@ -1,9 +1,9 @@
 include auto_fpga_build.mk
 
 # Add iob-soc software as a build dependency
-RUN_DEPS+=iob_soc_preboot.hex iob_soc_boot.hex iob_soc_firmware.hex
+RUN_DEPS+=iob_soc_bootrom.hex iob_soc_firmware.hex
 # Don't add firmware to BUILD_DEPS if we are not initializing memory since we don't want to rebuild the bitstream when we modify it.
-BUILD_DEPS+=iob_soc_preboot.hex iob_soc_boot.hex $(if $(filter $(INIT_MEM),1),iob_soc_firmware.hex)
+BUILD_DEPS+=iob_soc_bootrom.hex $(if $(filter $(INIT_MEM),1),iob_soc_firmware.hex)
 
 QUARTUS_SEED ?=5
 

diff --git a/hardware/fpga/quartus/cyclonev_gt_dk/board.tcl b/hardware/fpga/quartus/cyclonev_gt_dk/board.tcl
@@ -33,11 +33,11 @@ if {$IS_FPGA == "1"} {
     #set_location_assignment  PIN_AM23 -to led
     #set_instance_assignment -name IO_STANDARD "2.5-V" -to led
 
-    set_location_assignment  PIN_AE25 -to trap_o
-    set_instance_assignment -name IO_STANDARD "1.5-V" -to trap_o
+    #set_location_assignment  PIN_AE25 -to trap_o
+    #set_instance_assignment -name IO_STANDARD "1.5-V" -to trap_o
 
-    set_instance_assignment -name SLEW_RATE 1 -to trap_o
-    set_instance_assignment -name CURRENT_STRENGTH_NEW DEFAULT -to trap_o
+    #set_instance_assignment -name SLEW_RATE 1 -to trap_o
+    #set_instance_assignment -name CURRENT_STRENGTH_NEW DEFAULT -to trap_o
 
     #Uart
     set_location_assignment PIN_F10 -to txd_o

diff --git a/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py b/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py
@@ -52,13 +52,6 @@ def setup(py_params_dict):
                 {"name": "resetn", "direction": "input", "width": "1"},
             ],
         },
-        {
-            "name": "trap",
-            "descr": "CPU trap output",
-            "signals": [
-                {"name": "trap", "direction": "output", "width": "1"},
-            ],
-        },
         {
             "name": "rs232",
             "descr": "Serial port",
@@ -263,7 +256,6 @@ def setup(py_params_dict):
             },
             "connect": {
                 "clk_en_rst": "clk_en_rst",
-                "cpu_trap": "trap",
                 "rs232": "rs232_int",
                 "axi": "axi",
             },
@@ -305,6 +297,7 @@ def setup(py_params_dict):
         attributes_dict["blocks"] += [
             {
                 "core_name": "axi_interconnect_wrapper",
+                "name": "fpga_axi_interconnect_wrapper",
                 "instance_name": "axi_interconnect",
                 "instance_description": "Interconnect instance",
                 "parameters": {

diff --git a/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py b/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py
@@ -125,16 +125,6 @@ def setup(py_params_dict):
                 "type": "clk_en_rst",
             },
         },
-        {
-            "name": "cpu_trap",
-            "descr": "CPU trap",
-            "signals": [
-                {
-                    "name": "trap",
-                    "width": "1",
-                },
-            ],
-        },
         {
             "name": "rs232_int",
             "descr": "iob-soc uart interface",
@@ -285,7 +275,6 @@ def setup(py_params_dict):
             },
             "connect": {
                 "clk_en_rst": "clk_en_rst",
-                "cpu_trap": "cpu_trap",
                 "rs232": "rs232_int",
                 "axi": "axi",
             },

diff --git a/hardware/fpga/vivado/vivado_premap.tcl b/hardware/fpga/vivado/vivado_premap.tcl
@@ -86,5 +86,6 @@ if { $USE_EXTMEM > 0 } {
     read_verilog vivado/$BOARD/clock_wizard.v
     read_verilog vivado/$BOARD/iob_reset_sync.v
     read_verilog vivado/$BOARD/iob_r.v
+    read_verilog vivado/$BOARD/axi_ram.v
 
 }
diff --git a/hardware/modules/iob_soc_mwrap/iob_soc_mwrap.py b/hardware/modules/iob_soc_mwrap/iob_soc_mwrap.py
@@ -17,7 +17,7 @@ def setup(py_params_dict):
                 "name": "BOOT_HEXFILE",
                 "descr": "Bootloader file name",
                 "type": "P",
-                "val": '"iob_soc_boot"',
+                "val": '"iob_soc_bootrom"',
                 "min": "NA",
                 "max": "NA",
             },

diff --git a/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py b/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py
@@ -52,13 +52,6 @@ def setup(py_params_dict):
                 "subtype": "slave",
             },
         },
-        {
-            "name": "trap",
-            "descr": "CPU trap",
-            "signals": [
-                {"name": "trap", "direction": "output", "width": "1"},
-            ],
-        },
         {
             "name": "uart",
             "descr": "Testbench uart csrs interface",
@@ -194,7 +187,6 @@ def setup(py_params_dict):
             },
             "connect": {
                 "clk_en_rst": "clk_en_rst",
-                "cpu_trap": "trap",
                 "rs232": "rs232",
                 "axi": "axi",
             },
@@ -203,8 +195,10 @@ def setup(py_params_dict):
         },
         {
             "core_name": "iob_uart",
+            "name": "iob_uart_iob",
             "instance_name": "uart_tb",
             "instance_description": "Testbench uart core",
+            "csr_if": "iob",
             "connect": {
                 "clk_en_rst": "clk_en_rst",
                 "cbus": "uart",
@@ -213,6 +207,7 @@ def setup(py_params_dict):
         },
         {
             "core_name": "axi_interconnect_wrapper",
+            "name": "sim_axi_interconnect_wrapper",
             "instance_name": "axi_interconnect",
             "instance_description": "Interconnect instance",
             "parameters": {

diff --git a/hardware/simulation/sim_build.mk b/hardware/simulation/sim_build.mk
@@ -1,7 +1,7 @@
 include auto_sim_build.mk
 
 # Add iob-soc software as a build dependency
-HEX+=iob_soc_preboot.hex iob_soc_boot.hex iob_soc_firmware.hex
+HEX+=iob_soc_bootrom.hex iob_soc_firmware.hex
 
 ROOT_DIR :=../..
 include $(ROOT_DIR)/software/sw_build.mk

diff --git a/hardware/simulation/src/iob_soc_tb.cpp b/hardware/simulation/src/iob_soc_tb.cpp
@@ -110,13 +110,6 @@ int main(int argc, char **argv, char **env) {
 #endif
 
   while (1) {
-    if (dut->trap_o > 0) {
-      printf("\nTESTBENCH: force cpu trap exit\n");
-      cpu_char = 4;
-      fwrite(&cpu_char, sizeof(char), 1, soc2cnsl_fd);
-      fclose(soc2cnsl_fd);
-      break;
-    }
     while (!rxread_reg && !txread_reg) {
       rxread_reg = (char)iob_read(IOB_UART_RXREADY_ADDR, &uart_if);
       txread_reg = (char)iob_read(IOB_UART_TXREADY_ADDR, &uart_if);

diff --git a/hardware/simulation/src/iob_soc_tb.v b/hardware/simulation/src/iob_soc_tb.v
@@ -43,9 +43,6 @@ module iob_soc_tb;
    integer i = 0, n = 0;
    integer error, n_byte = 0;
 
-   //cpu trap signal
-   wire trap;
-
    /////////////////////////////////////////////
    // TEST PROCEDURE
    //
@@ -144,7 +141,6 @@ module iob_soc_tb;
       .clk_i (clk),
       .cke_i (1'b1),
       .arst_i(arst),
-      .trap_o(trap),
 
 `ifdef IOB_SOC_USE_ETHERNET
       .ethernet_iob_valid_i (ethernet_valid),
@@ -180,10 +176,4 @@ module iob_soc_tb;
 
    `include "iob_tasks.vs"
 
-   //finish simulation on trap
-   always @(posedge trap) begin
-      #10 $display("Found CPU trap condition");
-      $finish();
-   end
-
 endmodule