Generate internal CSR FIFOS (via python params); Add CSRs APB, AXI, AXIL support; Remove default pc-emul sources. #48
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TODO: Async fifos. Currently generated sync fifos have a "RW" "data" CSR. Therefore, they can be written/read to/from the CSRs and the core's interface. For the async fifo, the "data" CSR will most likely not be "RW".
Csrs module now supports new interfaces via `csr_if` parameter. Csrs module now contains an output of internal "IOb" signals for use in user logic. Upgrade py2hwsw version.
User specifies all sources. This is consistent with firmware sources.
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This change should solve the lib test failing: agrevin@f0611b3 |
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Included in PR IObundle/iob-soc#945