fix(vivado): Add missing include for axi_ram.v source

IObundle · Sep 10, 2024 · 265c1d9 · 265c1d9
1 parent d8d6abf
commit 265c1d9
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/hardware/fpga/vivado/vivado_premap.tcl b/hardware/fpga/vivado/vivado_premap.tcl
@@ -86,5 +86,6 @@ if { $USE_EXTMEM > 0 } {
     read_verilog vivado/$BOARD/clock_wizard.v
     read_verilog vivado/$BOARD/iob_reset_sync.v
     read_verilog vivado/$BOARD/iob_r.v
+    read_verilog vivado/$BOARD/axi_ram.v
 
 }