Minor Release v3.10.0

Pull Requests Since v3.9.0

Unlabeled

1. #180 - Bug fix for LCLS-II/evr/rtl/EvrV2Trigger.vhd

Pull Request Details

Bug fix for LCLS-II/evr/rtl/EvrV2Trigger.vhd

Author:	Larry Ruckman [email protected]
Date:	Tue Jan 14 14:10:27 2025 -0800
Pull:	#180 (17 additions, 28 deletions, 1 files changed)
Branch:	slaclab/v3.9.0-EvrV2Trigger-fifo-required

Notes:

Description

• #176 recreated a bug where no triggers generated when TRIG_DEPTH_C=0
• Remove NO_FIFO implementation from EvrV2Trigger; its always needed.

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Minor Release v3.9.0

Pull Requests Since v3.8.4

Unlabeled

1. #179 - adding TimingGty_fixedlat_Lcls1Only
2. #174 - Use SURF GtRxAlignCheck rather than local version

Pull Request Details

Use SURF GtRxAlignCheck rather than local version

Author:	Larry Ruckman [email protected]
Date:	Fri Jan 10 08:10:48 2025 -0800
Pull:	#174 (40 additions, 68 deletions, 10 files changed)
Branch:	slaclab/gtrxaligncheck-dev

Notes:

Make sure software rogue files still work.

Also output rxPmaResetDone from GTY wrapper, which can be used (inverted) to reset a clock manager receiving the recovered clock.

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adding TimingGty_fixedlat_Lcls1Only

Author:	Larry Ruckman [email protected]
Date:	Mon Jan 13 20:53:04 2025 -0800
Pull:	#179 (1629 additions, 11 deletions, 4 files changed)
Branch:	slaclab/TimingGty_fixedlat_Lcls1Only

Notes:

During the cameralink-gateway testing using the C1100 hardware (GTY+), we noticed that we would see a recoverRxClk for LCLS-II mode. But for LCLS-I mode, the recoverRxClk was zero MHz (not changing at all).

When I tried to using the "smurf" IP core (2.457.6 Gb/s), both LCLS-I and LCLS-II would be recoverRxClk of zero Hz. I even tried making a special 3.0 Gb/s (half way between LCLS-I and LCLS-II rates) and still see recoverRxClk of zero Hz for both LCLS-I and LCLS-II.

My theory is that the CPLL for the GTY+ (GTYE4) has a much narrowing operating range than Kintex Ultrascale GTH (GTHE3). This would explain why Mitch has to make this special GTY+ IP core for SMURF. At the end of the day, it looks like GTY can only support 1 mode of operation (not dual mode that we are use to with the AMC carrier GEN1) without going down the rabbit hole of using the DRP interface to replicate the GTY+ configuration..

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Patch Release v3.8.4

Pull Requests Since v3.8.3

Unlabeled

1. #176 - V3.8.3 trigger pipeline fix
2. #173 - Add Ruckus Flag to Load XCI Instead of DCP
3. #172 - Updating code comments for Ultrascale/Ultrascale+ GTs wrapper

Pull Request Details

Updating code comments for Ultrascale/Ultrascale+ GTs wrapper

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 25 11:10:48 2024 -0700
Pull:	#172 (4 additions, 3 deletions, 4 files changed)
Branch:	slaclab/stableClk-gt-comment

Notes:

Description

• StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)

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Add Ruckus Flag to Load XCI Instead of DCP

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 2 09:59:32 2024 -0700
Pull:	#173 (29 additions, 19 deletions, 3 files changed)
Branch:	slaclab/xci-option

Notes:

The ruckus.tcl files that load IP cores now look for an LCLS_TIMING_XCI environment variable.
If it is set to 1, then the XCI file is loaded instead of the DCP.

This is useful in simulation. For example, add this line to the target makefile so that the XCI is loaded when building the project for VCS simulation.

vcs: export LCLS_TIMING_XCI=1

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V3.8.3 trigger pipeline fix

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 14 12:48:51 2024 -0800
Pull:	#176 (90 additions, 50 deletions, 1 files changed)
Branch:	slaclab/v3.8.3-trigger-pipeline-fix

Notes:

I fixed a long standing problem (and a newly discovered one) where changing the trigger configuration parameters, namely delay and width, while the trigger pipeline is enabled causes errors that can overflow the pipeline (negative delay change) or produce the wrong delay (width change).

The one cycle push of delay onto the fifo was replaced with two pushes, each representing a transition of the output trigger state.

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Patch Release v3.8.3

Pull Requests Since v3.8.2

Unlabeled

1. #170 - Update TimingGtCoreWrapper.vhd

Pull Request Details

Update TimingGtCoreWrapper.vhd

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 20 09:42:42 2024 -0700
Pull:	#170 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/ruck314/RX-RX_EQUALIZER_G

Notes:

Description

• Updating the RX RX_EQUALIZER_G from DFE to LPM
• Related to slaclab/evr-card-g2#11

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Patch Release v3.8.2

Pull Requests Since v3.8.1

Unlabeled

1. #166 - Update timing_ci.yml
2. #167 - updated clktime_186MHz
3. #169 - added ClockTime ports

Pull Request Details

Update timing_ci.yml

Author:	Larry Ruckman [email protected]
Date:	Thu Jun 27 15:39:48 2024 -0700
Pull:	#166 (15 additions, 80 deletions, 1 files changed)
Branch:	slaclab/ruck314-patch-1

Notes:

Description

• Using the reusable YAML CI scripts

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updated clktime_186MHz

Author:	Larry Ruckman [email protected]
Date:	Wed Aug 14 08:27:37 2024 -0700
Pull:	#167 (5 additions, 5 deletions, 2 files changed)
Branch:	slaclab/tcore_tokenizer

Notes:

Updated the name of the module ClockTime

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added ClockTime ports

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 16 12:49:51 2024 -0700
Pull:	#169 (2 additions, 2 deletions, 1 files changed)
Branch:	slaclab/tcore_tokenizerxx
Issues:	#169

Notes:

Added ports: "steps, remainder, divisor" to ClockTime.vhd

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Patch Release v3.8.1

Pull Requests Since v3.8.0

Unlabeled

1. #164 - V3.7.0 streamtx evr

Pull Request Details

V3.7.0 streamtx evr

Author:	Matt Weaver [email protected]
Date:	Mon Mar 11 10:39:57 2024 -0500
Pull:	#164 (32 additions, 22 deletions, 2 files changed)
Branch:	slaclab/v3.7.0-streamtx-evr

Notes:

Description

• Modify TimingStreamTx to be consistent with EVG output. EVRs can tell the difference
• Add AC sampling configuration registers

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Minor Release v3.8.0

Pull Requests Since v3.7.7

Unlabeled

1. #162 - Fix Rx issues

Pull Request Details

Fix Rx issues

Author:	Matt Weaver [email protected]
Date:	Tue Dec 5 14:05:38 2023 -0600
Pull:	#162 (1876 additions, 2982 deletions, 11 files changed)
Branch:	slaclab/debuggingTimingRx

Notes:

Fixes a reset scheme issue on the GTH Rx alignment process

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Patch Release v3.7.7

Description

• CI Anaconda bug fix

Full Changelog: v3.7.4...v3.7.7

Patch Release v3.7.4

Full Changelog: v3.7.3...v3.7.4

Pull Requests Since v3.7.3

Unlabeled

1. #160 - Fixes for ultrascale+gth
2. #159 - Updating smurf/TimingGty_fixedlat.[xci,dcp]

Pull Request Details

Updating smurf/TimingGty_fixedlat.[xci,dcp]

Author:	Larry Ruckman [email protected]
Date:	Sat Jul 8 10:03:35 2023 -0700
Pull:	#159 (8 additions, 8 deletions, 2 files changed)
Branch:	slaclab/TimingGty_fixedlat-smurf-update

Notes:

Description

• adding cpllrefclksel_in & gtgrefclk_in ports to match LCLS-II API

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Fixes for ultrascale+gth

Author:	Larry Ruckman [email protected]
Date:	Mon Jul 10 09:47:46 2023 -0700
Pull:	#160 (109 additions, 42 deletions, 5 files changed)
Branch:	slaclab/fixesForUltrascale+gth

Notes:

These were the changes I needed to make on the Ultrascale+ GTH for it to work with the detector boards.
Key changes:
1 set the clock to 156.25MHz to match the clock used
2 set SIM_CPLL_CAL_BYPASS to true
3 Timing receiver module now gets a new generic that selects from gty and gth

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Patch Release v3.7.3

Pull Requests Since v3.7.2

Unlabeled

1. #157 - V3.6.3 trigfifo flush

Pull Request Details

V3.6.3 trigfifo flush

Author:	Larry Ruckman [email protected]
Date:	Tue Jun 20 13:03:07 2023 -0700
Pull:	#157 (19 additions, 9 deletions, 4 files changed)
Branch:	slaclab/v3.6.3-trigfifo-flush

Notes:

Reset the serial delay FIFOs when an overflow is detected. Also, allow more status count registers to roll over.

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