Merge pull request #177 from slaclab/pre-release

Release Candidate v3.9.0
slaclab · Jan 14, 2025 · 6ed8c16 · 6ed8c16
2 parents 7ee3709 + f36309f
commit 6ed8c16
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Showing 13 changed files with 1,697 additions and 90 deletions.
diff --git a/LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd b/LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd
@@ -342,9 +342,7 @@ begin  -- rtl
   Out_Trigger: for i in 0 to TriggerOutputs-1 generate
      U_Trig : entity lcls_timing_core.EvrV2Trigger
         generic map ( TPD_G    => TPD_G,
-                      CHANNELS_C => ReadoutChannels,
-                      --DEBUG_C    => (i<1) )
-                      DEBUG_C    => false )
+                      CHANNELS_C => ReadoutChannels)
         port map (    clk      => evrClk,
                       rst      => evrRst,
                       config   => triggerConfigS(i),

diff --git a/LCLS-II/evr/rtl/EvrV2Module.vhd b/LCLS-II/evr/rtl/EvrV2Module.vhd
@@ -177,8 +177,7 @@ begin  -- rtl
      U_Trig : entity lcls_timing_core.EvrV2Trigger
         generic map ( TPD_G        => TPD_G,
                       CHANNELS_C   => NCHANNELS_G,
-                      TRIG_DEPTH_C => TRIG_DEPTH_G,
-                      DEBUG_C      => false )
+                      TRIG_DEPTH_C => TRIG_DEPTH_G)
         port map (    clk        => evrClk,
                       rst        => evrRst,
                       config     => triggerConfig(i),

diff --git a/LCLS-II/evr/rtl/EvrV2Trigger.vhd b/LCLS-II/evr/rtl/EvrV2Trigger.vhd
@@ -48,7 +48,7 @@ end EvrV2Trigger;
 architecture rtl of EvrV2Trigger is
 
    type PushState is (DISABLED_S, ENABLED_S, ARMED_S, PUSHING_S);
-  
+
    type RegType is record
      fifo_delay     : slv(TRIG_WIDTH_C-1 downto 0);      -- clks until trigger fifo is empty
      push_state     : PushState;
@@ -164,7 +164,7 @@ begin
 
       -- Precalculate
       v.push_delay := config.delay(TRIG_WIDTH_C-1 downto 0) + config.width(TRIG_WIDTH_C-1 downto 0) - 1;
-      
+
       case r.push_state is
         when DISABLED_S =>
           if config.enabled = '1' then

diff --git a/LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci b/LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci
@@ -821,28 +821,13 @@
         "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ]
       },
-      "project_parameters": {
-        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
-        "BASE_BOARD_PART": [ { "value": "" } ],
-        "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xcku15p" } ],
-        "PACKAGE": [ { "value": "ffva1156" } ],
-        "PREFHDL": [ { "value": "VHDL" } ],
-        "SILICON_REVISION": [ { "value": "" } ],
-        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
-        "SPEEDGRADE": [ { "value": "-2" } ],
-        "STATIC_POWER": [ { "value": "" } ],
-        "TEMPERATURE_GRADE": [ { "value": "E" } ],
-        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
-        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
-      },
       "runtime_parameters": {
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
         "IPREVISION": [ { "value": "15" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_extref" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
-        "SHAREDDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_extref" } ],
+        "SHAREDDIR": [ { "value": "." } ],
         "SWVERSION": [ { "value": "2022.2" } ],
         "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
       }

diff --git a/LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci b/LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci
@@ -821,26 +821,11 @@
         "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ]
       },
-      "project_parameters": {
-        "ARCHITECTURE": [ { "value": "kintexuplus" } ],
-        "BASE_BOARD_PART": [ { "value": "" } ],
-        "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xcku15p" } ],
-        "PACKAGE": [ { "value": "ffva1156" } ],
-        "PREFHDL": [ { "value": "VHDL" } ],
-        "SILICON_REVISION": [ { "value": "" } ],
-        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
-        "SPEEDGRADE": [ { "value": "-2" } ],
-        "STATIC_POWER": [ { "value": "" } ],
-        "TEMPERATURE_GRADE": [ { "value": "E" } ],
-        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
-        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
-      },
       "runtime_parameters": {
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
         "IPREVISION": [ { "value": "15" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_fixedlat" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
         "SHAREDDIR": [ { "value": "." } ],
         "SWVERSION": [ { "value": "2022.2" } ],

diff --git a/LCLS-II/gthUltraScale+/ruckus.tcl b/LCLS-II/gthUltraScale+/ruckus.tcl
@@ -4,7 +4,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 if { $::env(VIVADO_VERSION) >= 2022.2} {
    loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"
 
-   if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
+   if { [info exists ::env(LCLS_TIMING_GTH_XCI)] != 0 && $::env(LCLS_TIMING_GTH_XCI) == 1 } {
        loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
        loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
    } else {

diff --git a/LCLS-II/gthUltraScale/ruckus.tcl b/LCLS-II/gthUltraScale/ruckus.tcl
@@ -5,7 +5,7 @@ if { $::env(VIVADO_VERSION) >= 2016.4 } {
 
    loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"
 
-   if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
+   if { [info exists ::env(LCLS_TIMING_GTH_XCI)] != 0 && $::env(LCLS_TIMING_GTH_XCI) == 1 } {
        loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
        loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
    } else {

diff --git a/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat_Lcls1Only.dcp b/LCLS-II/gtyUltraScale+/coregen/TimingGty_fixedlat_Lcls1Only.dcp