Patch Release

Pull Requests

1. #102 - v3.0.3 release candidate
2. #101 - adding flake8 to .travis.yml

Pull Request Details

v3.0.3 release candidate

Author:	Larry Ruckman [email protected]
Date:	Fri Feb 28 08:49:23 2020 -0800
Pull:	#102 (409 additions, 426 deletions, 19 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• adding flake8 to .travis.yml #101

---

adding flake8 to .travis.yml

Author:	Larry Ruckman [email protected]
Date:	Thu Feb 20 14:18:19 2020 -0800
Pull:	#101 (409 additions, 426 deletions, 19 files changed)
Branch:	slaclab/flake8

Notes:

Description

• Added python linter to travic CI
• Fixed some bugs in the python code
  • Caught by the linter
• Some mics code header clean up

---

Patch Release

Pull Requests

1. #100 - v3.0.2 release candidate
2. #98 - Add anaconda recipe
3. #99 - TimingGtCoreWrapper with external ref clock buffer

Pull Request Details

v3.0.2 release candidate

Author:	Benjamin Reese [email protected]
Date:	Thu Feb 13 12:42:41 2020 -0800
Pull:	#100 (353 additions, 222 deletions, 108 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Add anaconda recipe #98
• TimingGtCoreWrapper with external ref clock buffer #99

---

Add anaconda recipe

Author:	Larry Ruckman [email protected]
Date:	Wed Feb 12 08:44:54 2020 -0800
Pull:	#98 (121 additions, 0 deletions, 5 files changed)
Branch:	slaclab/conda_recipe

Notes:

---

TimingGtCoreWrapper with external ref clock buffer

Author:	Larry Ruckman [email protected]
Date:	Wed Feb 12 15:06:14 2020 -0800
Pull:	#99 (50 additions, 29 deletions, 1 files changed)
Branch:	slaclab/wave8-dev

Notes:

Added an option for external IBUFDS_GTE2. Fixed a VCS compile error.

---

Patch Release v3.0.1

Pull Requests

1. #96 - Update submodule locks
2. Check for Vivado version 2019.1 (or later)

Pull Request Details

Update submodule locks

Author:	Benjamin Reese [email protected]
Date:	Thu Feb 6 15:28:29 2020 -0800
Pull:	#96 (2 additions, 2 deletions, 1 files changed)
Branch:	slaclab/submodule-locks

Notes:

Require surf v2.0.6 or later and ruckus v2.1.2 or later

---

Patch Release

Pull Requests

1. #78 - Revamp Extension Bus Interface
2. #95 - adding gtx7/TimingGtCoreWrapper
3. #94 - Partition addr removal
4. #91 - LCLS-I/evr/EvrV1CoreIsrCtrl.vhd bug fix
5. #92 - TimingMsgDelay.vhd bug fix

Pull Request Details

Revamp Extension Bus Interface

Author:	Benjamin Reese [email protected]
Date:	Tue Feb 4 12:56:40 2020 -0800
Pull:	#78 (1028 additions, 1081 deletions, 20 files changed)
Branch:	slaclab/extension-dev

Notes:

Major interface-breaking Changes

The timing "extension" interface has been revamped.

Dependence on an external TimingExtnPkg has been removed, and there is no more TimingExtType. The extn field of the TimingBusType is now an array of 15 512-bit extension messages, each with a valid to indicate presence. This is makes for an enormous array, but nearly all of it will optimize away when not used. Most applications will use only 1 or 2 of the 15 possible extension streams.

Other interface changes

Renamed the timingPhy output of TimingCore to tpgMiniTimingPhy to better indicate it's source.
Renamed several fields to remove confusing abbreviations. E.g. extn -> extension

Other changes

Updated TimingMessage <-> SLV conversion functions.

---

adding gtx7/TimingGtCoreWrapper

Author:	Larry Ruckman [email protected]
Date:	Tue Feb 4 13:29:11 2020 -0800
Pull:	#95 (350 additions, 0 deletions, 3 files changed)
Branch:	slaclab/gtx7

Notes:

Description

• Used with Kintex-7 FPGAs
• Mostly copied from https://github.com/slaclab/evr-card-g2/blob/b48a33be9147a493835a52f29a620d6e3882bebe/firmware/common/EvrCardG2/general/rtl/EvrCardG2Gtx.vhd

---

Partition addr removal

Author:	Larry Ruckman [email protected]
Date:	Sat Jan 18 23:09:28 2020 -0800
Pull:	#94 (0 additions, 9 deletions, 1 files changed)
Branch:	slaclab/partitionAddr_removal

Notes:

Remove the remainder of partitionAddr signal from interfaces.

---

LCLS-I/evr/EvrV1CoreIsrCtrl.vhd bug fix

Author:	Larry Ruckman [email protected]
Date:	Fri Jan 17 16:46:04 2020 -0800
Pull:	#91 (3 additions, 3 deletions, 1 files changed)
Branch:	slaclab/EvrV1CoreIsrCtrl-patch

Notes:

Description

• LCLS-I/evr/EvrV1CoreIsrCtrl.vhd bug fix

---

TimingMsgDelay.vhd bug fix

Author:	Larry Ruckman [email protected]
Date:	Fri Jan 17 16:46:11 2020 -0800
Pull:	#92 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/TimingMsgDelay-patch

Notes:

Description

• TimingMsgDelay.vhd bug fix

---

Major Release

Pull Requests

1. #86 - Release Candidate 2.0.0
2. #79 - Adding TravisCI
3. #82 - Refactor for use of VHDL Libraries
4. #75 - Merge updated support for embedded streams.
5. #81 - Move BldAxiStream module to amc-carrier-core repo
6. #89 - code header update
7. #84 - Refactor for MEMORY_TYPE_G generic in SURF RAMs
8. #87 - remove use work.all;
9. #80 - Fix DCP files so that GT locations are no longer constrained
10. #88 - Remove USE_BUILT_IN_G and USE_DSP_48_G
11. #76 - Reset ignored by TimingSerializer, TimingDeserializer, TimingStreamTx
12. #85 - Update ruckus.tcl

Pull Request Details

Release Candidate 2.0.0

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 21 15:21:44 2019 -0800
Pull:	#86 (3945 additions, 1326 deletions, 78 files changed)
Branch:	slaclab/pre-release

Notes:

Pull Requests

1. #79 - Adding TravisCI
2. #82 - Refactor for use of VHDL Libraries
3. #75 - Merge updated support for embedded streams.
4. #81 - Move BldAxiStream module to amc-carrier-core repo
5. #84 - Refactor for MEMORY_TYPE_G generic in SURF RAMs
6. #87 - remove use work.all;
7. #80 - Fix DCP files so that GT locations are no longer constrained
8. #76 - Reset ignored by TimingSerializer, TimingDeserializer, TimingStreamTx
9. #85 - Update ruckus.tcl
10. #89 - code header update

---

Adding TravisCI

Author:	Larry Ruckman [email protected]
Date:	Fri Oct 18 12:17:57 2019 -0700
Pull:	#79 (2746 additions, 2 deletions, 8 files changed)
Branch:	slaclab/travis-Byte-compile-Python

Notes:

Description

• Travis recipe does the following:
  • python syntax error checking
  • VHDL syntax error checking
  • Doxygen firmware documentation

---

Refactor for use of VHDL Libraries

Author:	Benjamin Reese [email protected]
Date:	Tue Nov 19 13:22:26 2019 -0800
Pull:	#82 (596 additions, 394 deletions, 65 files changed)
Branch:	slaclab/vhdl-lib

Notes:

This change refactors the code to expect SURFmodules and packages to be in surf VHDL libraries.

It also refactors the code to place it's own modules and packages in an amc_carrier_core library.

This PR can't be merged until the corresponding changes in surf are merged.

• slaclab/surf#541

---

Merge updated support for embedded streams.

Author:	Larry Ruckman [email protected]
Date:	Mon Mar 18 09:27:50 2019 -0700
Pull:	#75 (567 additions, 64 deletions, 10 files changed)
Branch:	slaclab/ESLTIMING-20
Jira:	https://jira.slac.stanford.edu/issues/ESLTIMING-20

Notes:

Description

Merge updated support for embedded streams.

JIRA

ESLTIMING-20

---

Move BldAxiStream module to amc-carrier-core repo

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 31 13:47:38 2019 -0700
Pull:	#81 (0 additions, 462 deletions, 2 files changed)
Branch:	slaclab/move-BldAxiStream

Notes:

The BldAxiStream module had a dependency on amc-carrier-core, and was only even instantiated by the BSA engine. It has been moved to the amc-carrier-core repository.

slaclab/amc-carrier-core#237

---

code header update

Author:	Benjamin Reese [email protected]
Date:	Thu Nov 21 14:54:57 2019 -0800
Pull:	#89 (2 additions, 337 deletions, 58 files changed)
Branch:	slaclab/code-header-update

Notes:

Description

• Updating the VHDL coder header to our current standard

---

Refactor for MEMORY_TYPE_G generic in SURF RAMs

Author:	Benjamin Reese [email protected]
Date:	Wed Nov 20 10:51:08 2019 -0800
Pull:	#84 (37 additions, 46 deletions, 7 files changed)
Branch:	slaclab/memory_type_g

Notes:

---

remove use work.all;

Author:	Benjamin Reese [email protected]
Date:	Thu Nov 21 11:54:03 2019 -0800
Pull:	#87 (0 additions, 23 deletions, 20 files changed)
Branch:	slaclab/remove-work-all

Notes:

Description

• As part of the refactoring, removed all use of use work.all;

---

Fix DCP files so that GT locations are no longer constrained

Author:	Benjamin Reese [email protected]
Date:	Tue Nov 19 15:48:39 2019 -0800
Pull:	#80 (8 additions, 8 deletions, 4 files changed)
Branch:	slaclab/fix-dcp-cons

Notes:

Projects that had multiple TimingGt cores at different locations were getting constraint conflicts due to constraints that were set on the DCP files. The DCP files have been fixed to remove these constraints.

---

Remove USE_BUILT_IN_G and USE_DSP_48_G

Author:	Benjamin Reese [email protected]
Date:	Thu Nov 21 12:14:00 2019 -0800
Pull:	#88 (2 additions, 8 deletions, 2 files changed)
Branch:	slaclab/refactor

Notes:

---

Reset ignored by TimingSerializer, TimingDeserializer, TimingStreamTx

Author:	Larry Ruckman [email protected]
Date:	Wed May 1 01:49:39 2019 -0700
Pull:	#76 (3 additions, 3 deletions, 3 files changed)
Branch:	slaclab/ESLTIMING-22
Jira:	https://jira.slac.stanford.edu/issues/ESLTIMING-22

Notes:

The combinatorial code in these modules contained a bug which renders
the reset signal ineffective.

See jira ticket

---

Update ruckus.tcl

Author:	Benjamin Reese [email protected]
Date:	Thu Nov 21 11:12:53 2019 -0800
Pull:	#85 (2 additions, 2 deletions, 1 files changed)
Branch:	slaclab/SUBMODULE_LOCKS

Notes:

Description

• Update SUBMODULE_LOCKS for the refactoring of FW libs

---

Patch Release

Pull Requests

1. #74 - v1.12.6 release candidate
2. #73 - optimizing the EvrV2CoreTriggers.vhd memory address space usage
3. #72 - VCS Bug Fixes

Pull Request Details

v1.12.6 release candidate

Author:	Larry Ruckman [email protected]
Date:	Thu Mar 14 11:35:50 2019 -0700
Pull:	#74 (458 additions, 1219 deletions, 32 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• VCS Bug fixes (#72)
• Optimized the EvrV2CoreTriggers.vhd memory address space usage (#73)

Note

• This version requires that the EVR PCIe card sets the (EVR_CARD_G=true)

---

optimizing the EvrV2CoreTriggers.vhd memory address space usage

Author:	Larry Ruckman [email protected]
Date:	Thu Mar 14 10:23:30 2019 -0700
Pull:	#73 (368 additions, 1209 deletions, 28 files changed)
Branch:	slaclab/EvrV2CoreTriggers-update

Notes:

Description

• optimizing the EvrV2CoreTriggers.vhd memory address space usage
• While the AMC carrier is 32-bit of address space, the PCIe applications have a BAR0 of 24-bits, which makes it difficult to fix the EvrV2CoreTriggers with all the other AXI-Lite modules on BAR0

---

VCS Bug Fixes

Author:	Larry Ruckman [email protected]
Date:	Tue Feb 26 15:18:28 2019 -0800
Pull:	#72 (12 additions, 4 deletions, 3 files changed)
Branch:	slaclab/vcs-bug-fix

Notes:

Description

• resolved VCS error in TPGMiniStream.vhd (67fc622#comments)
• resolved VCS error in GthRxAlignCheck.vhd (542e71e#comments)
• resolved VCS error in TimingExtnPkg.vhd (1838b4c#comments)

---

Patch Release

Pull Requests

1. #71 - v1.12.5 release candidate

Pull Request Details

v1.12.5 release candidate

Author:	Larry Ruckman [email protected]
Date:	Thu Feb 7 08:18:05 2019 -0800
Pull:	#71 (17 additions, 9 deletions, 3 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• updating submodule locks
• python updates
• exposing AxiLiteConfig addrBits and DRP offset as generics in LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd

---

Patch Release

Pull Requests

1. #70 - v1.12.4 release candidate

Pull Request Details

v1.12.4 release candidate

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 8 11:26:03 2018 -0800
Pull:	#70 (3 additions, 3 deletions, 1 files changed)
Branch:	slaclab/pre-release

Notes:

Description

bug fixes for SURF v1.9.0

---

Patch Release

Pull Requests

1. #69 - v1.12.3 release candidate

Pull Request Details

v1.12.3 release candidate

Author:	Larry Ruckman [email protected]
Date:	Thu Nov 8 09:20:25 2018 -0800
Pull:	#69 (75 additions, 35 deletions, 3 files changed)
Branch:	slaclab/pre-release

Notes:

Description

bug fixes for SURF v1.9.0

---

Patch Release

Pull Requests

1. #68 - v1.12.2 release candidate
2. #67 - Add EVRv2 channel and trigger PyRogue
3. #66 - ESLCOMMON-234
4. #65 - f in False needs capitalization

Pull Request Details

v1.12.2 release candidate

Author:	Larry Ruckman [email protected]
Date:	Tue Oct 16 08:42:14 2018 -0700
Pull:	#68 (295 additions, 4 deletions, 6 files changed)
Branch:	slaclab/pre-release

Notes:

Description

• Fixed syntax bug in some python
• Removed '.lfsconfig' file
• Add EVRv2 channel and trigger PyRogue modules

---

Add EVRv2 channel and trigger PyRogue

Author:	Larry Ruckman [email protected]
Date:	Mon Oct 8 14:00:14 2018 -0700
Pull:	#67 (259 additions, 1 deletions, 4 files changed)
Branch:	slaclab/cryo-dev

Notes:

Add EVRv2 channel and trigger PyRogue modules

---

ESLCOMMON-234

Author:	Larry Ruckman [email protected]
Date:	Mon Oct 1 08:46:38 2018 -0700
Pull:	#66 (0 additions, 3 deletions, 1 files changed)
Branch:	slaclab/ESLCOMMON-234
Jira:	https://jira.slac.stanford.edu/issues/ESLCOMMON-234

Notes:

A while ago an '.lfsconfig' file was erroneously pushed. This was meant for local use only.

---

f in False needs capitalization

Author:	Larry Ruckman [email protected]
Date:	Fri Aug 31 13:37:01 2018 -0700
Pull:	#65 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/TimeToolDevelopment

Notes:

Description

f in False needs capitalization for python

---