Merge pull request #90 from slaclab/pre-release

Release Candidate v3.0.0

LCLS-I/evr/EvrV1CoreIsrCtrl.vhd

@@ -154,7 +154,7 @@ architecture rtl of EvrV1CoreIsrCtrl is
       axilReadSlave  : AxiLiteReadSlaveType;
       axilWriteSlave : AxiLiteWriteSlaveType;
       txMaster       : AxiStreamMasterType;
-      req            : AxiLiteMasterReqType;
+      req            : AxiLiteReqType;
       state          : StateType;
    end record RegType;
    constant REG_INIT_C : RegType := (
@@ -168,14 +168,14 @@ architecture rtl of EvrV1CoreIsrCtrl is
       axilReadSlave  => AXI_LITE_READ_SLAVE_INIT_C,
       axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C,
       txMaster       => AXI_STREAM_MASTER_INIT_C,
-      req            => AXI_LITE_MASTER_REQ_INIT_C,
+      req            => AXI_LITE_REQ_INIT_C,
       state          => IDLE_S);
 
    signal r   : RegType := REG_INIT_C;
    signal rin : RegType;
 
    signal txSlave : AxiStreamSlaveType;
-   signal ack     : AxiLiteMasterAckType;
+   signal ack     : AxiLiteAckType;
 
 begin
 

LCLS-II/core/rtl/BsaControl.vhd

@@ -1,9 +1,5 @@
 -------------------------------------------------------------------------------
--- Title         : BsaControl
--- Project       : LCLS-II Timing Pattern Generator
--------------------------------------------------------------------------------
--- Author        : Matt Weaver, [email protected]
--- Created       : 07/17/2015
+-- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description:
 -- Translation of BSA DEF to control bits in timing pattern
@@ -16,9 +12,6 @@
 -- may be copied, modified, propagated, or distributed except according to 
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------
--- Modification history:
--- 07/17/2015: created.
--------------------------------------------------------------------------------
 library ieee;
 
 library lcls_timing_core;

LCLS-II/core/rtl/BsaControlv2.vhd

@@ -1,9 +1,5 @@
 -------------------------------------------------------------------------------
--- Title         : BsaControl
--- Project       : LCLS-II Timing Pattern Generator
--------------------------------------------------------------------------------
--- Author        : Matt Weaver, [email protected]
--- Created       : 07/17/2015
+-- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description:
 -- Translation of BSA DEF to control bits in timing pattern
@@ -17,9 +13,6 @@
 -- may be copied, modified, propagated, or distributed except according to 
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------
--- Modification history:
--- 07/17/2015: created.
--------------------------------------------------------------------------------
 library ieee;
 
 library lcls_timing_core;

LCLS-II/core/rtl/CtrControl.vhd

@@ -1,9 +1,5 @@
 -------------------------------------------------------------------------------
--- Title         : CtrControl
--- Project       : LCLS-II Timing Pattern Generator
--------------------------------------------------------------------------------
--- Author        : Matt Weaver, [email protected]
--- Created       : 07/17/2015
+-- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description:
 -- Translation of BSA DEF to control bits in timing pattern
@@ -17,9 +13,6 @@
 -- may be copied, modified, propagated, or distributed except according to 
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------
--- Modification history:
--- 07/17/2015: created.
--------------------------------------------------------------------------------
 library ieee;
 
 library lcls_timing_core;

LCLS-II/core/rtl/EventSelect.vhd

@@ -1,9 +1,5 @@
 -------------------------------------------------------------------------------
--- Title         : EventSelect
--- Project       : LCLS-II Timing Pattern Generator
--------------------------------------------------------------------------------
--- Author        : Matt Weaver, [email protected]
--- Created       : 03/07/2016
+-- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description:
 -- Translation of BSA DEF to control bits in timing pattern
@@ -16,9 +12,6 @@
 -- may be copied, modified, propagated, or distributed except according to 
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------
--- Modification history:
--- 03/07/2016: created.
--------------------------------------------------------------------------------
 library ieee;
 
 library lcls_timing_core;

LCLS-II/core/rtl/GthRxAlignCheck.vhd

@@ -3,11 +3,11 @@
 -------------------------------------------------------------------------------
 -- Description: GTH RX Byte Alignment Checker module
 -------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
+-- This file is part of 'LCLS2 Timing Core'.
 -- It is subject to the license terms in the LICENSE.txt file found in the 
 -- top-level directory of this distribution and at: 
 --    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
--- No part of 'SLAC Firmware Standard Library', including this file, 
+-- No part of 'LCLS2 Timing Core', including this file, 
 -- may be copied, modified, propagated, or distributed except according to 
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------

LCLS-II/core/rtl/TPGMini.vhd

@@ -113,7 +113,7 @@ begin
   streamIds <= istreamIds;
   iiadvance <= advance  when STREAM_INTF=true else
                iadvance;
-  fiducial  <= baseEnabled(0);
+  fiducial  <= baseEnable;
 
   -- Dont know about these inputs yet
   frame.bcsFault <= (others => '0');

LCLS-II/core/rtl/TPGNotify.vhd

@@ -1,9 +1,5 @@
-------------------------------------------------------------------------------
--- Title         : Timing pattern generator
--- Project       : LCLS-II Timing System
 -------------------------------------------------------------------------------
--- Author        : Matt Weaver, [email protected]
--- Created       : 05/19/2016
+-- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description:
 -------------------------------------------------------------------------------
@@ -15,9 +11,6 @@
 -- may be copied, modified, propagated, or distributed except according to 
 -- the terms contained in the LICENSE.txt file.
 -------------------------------------------------------------------------------
--- Modification history:
--- 09/15/2015: created.
--------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;

LCLS-II/core/rtl/TPGPkg.vhd

@@ -1,7 +1,7 @@
 -------------------------------------------------------------------------------
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
--- Description: Package of constants and record definitions for the Timing Geneartor.
+-- Description: Package of constants and record definitions for the Timing Generator.
 -------------------------------------------------------------------------------
 -- This file is part of 'LCLS2 Timing Core'.
 -- It is subject to the license terms in the LICENSE.txt file found in the