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Releases: jbilander/ReAgnus-MegAChip

Rev. 2C

13 May 21:26
@jbilander jbilander
v2c
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Rev. 2C Pre-release
Pre-release

Rev. 2C

Fixed with a 1.8V LDO voltage regulator to supply VCCIO3 with 1.8V (pSRAM-requirement).
Many signals relocated to bank 0 (3V3) instead of bank 3 that is now 1.8V.

A pull-up resistor (to 3V3) added for JTAG TDO-signal.

Assets 3
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Rev. 2A

18 Apr 19:58
@jbilander jbilander
v2a
1555559
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Rev. 2A Pre-release
Pre-release

Rev. 2A

ReAgnus-MegAChip design using a Gowin FPGA GW1NR-UV9LQ144PC6/I5 with embedded 64Mbit 16-bit PSRAM.

PCB changed to a 4-layer stackup and re-routed.

FET level shifters was changed to TVSOP-48 and CBT instead of CBTD type to lower the cost and ease routing.

4.3 LDO Voltage regulator added as power supply to the CBTs (for level shifting to 3.3V).

A GND Mounting-hole (M2 size) was added for proper grounding via a ring lug connector to Motherboard via jumper-wire.

Not tested yet!

Assets 3
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