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Rev. 2A

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@jbilander jbilander released this 18 Apr 19:58
· 25 commits to main since this release
v2a
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Rev. 2A

ReAgnus-MegAChip design using a Gowin FPGA GW1NR-UV9LQ144PC6/I5 with embedded 64Mbit 16-bit PSRAM.

PCB changed to a 4-layer stackup and re-routed.

FET level shifters was changed to TVSOP-48 and CBT instead of CBTD type to lower the cost and ease routing.

4.3 LDO Voltage regulator added as power supply to the CBTs (for level shifting to 3.3V).

A GND Mounting-hole (M2 size) was added for proper grounding via a ring lug connector to Motherboard via jumper-wire.

Not tested yet!

Assets 3
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