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Issues: chipsalliance/fpga-interchange-tests
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[nextpnr-fpga-interchange] Incorrect LUT INIT causing CRITICAL WARNINGS in Vivado
#126
opened Jul 28, 2022 by
clavin-xlnx
[nextpnr_fpga_interchange] Fails to properly place and route a design with hierarchy
#124
opened Jul 21, 2022 by
clavin-xlnx
[nextpnr_fpga_interchange] Fails when encountering unsupported XDC commands, provides warnings for others
#123
opened Jul 21, 2022 by
clavin-xlnx
[nextpnr_fpga_interchange] ERROR: Assert ctx->checkRoutedDesign() failed
#122
opened Jul 21, 2022 by
clavin-xlnx
A Tcl script that can take an arbitrary netlist and use Vivado to create pin placements
#121
opened Jul 21, 2022 by
clavin-xlnx
[nextpnr_fpga_interchange] Proceed with place and route despite missing pin placement constraints
#120
opened Jul 21, 2022 by
clavin-xlnx
Larger designs end up in netlist traversal limit being reached
bug
Something isn't working
#76
opened Sep 16, 2021 by
acomodi
Site LUT mapping cache error
bug
Something isn't working
invalid
This doesn't seem right
#75
opened Sep 16, 2021 by
acomodi
Issue with the rapidyaml Python package
bug
Something isn't working
#56
opened Jul 30, 2021 by
mkurc-ant
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