Site LUT mapping cache error

[acomodi]

There is an error corresponding to the LUT mapping cache that is triggered mostly for larger designs, probably due to a higher cell density.

The error is the following:

Info: Site LUT mapping cache stats:
Info:     miss ratio: 7.4%
Info:     peak size : 2412MB (2103609 items)
terminate called after throwing an instance of 'nextpnr_fpga_interchange::assertion_failure'
  what():  Assertion failure: map_luts_in_site(site_info, &blocked_wires) (/data/interchange/nextpnr/fpga_interchange/site_router.cc:1413)

After some debugging, it seems that some LUT map cache entries need to get updated or at least the cache key needs to be a bit more specific to cover more combinations, as at the moment, it might happen that in a site, something is changing that makes the cache entry invalid.