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riscv: fix mtvec address field #225

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riscv: fix mtvec address field #225

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1 change: 1 addition & 0 deletions riscv/CHANGELOG.md
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Expand Up @@ -25,6 +25,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

- Fixed `sip::set_ssoft` and `sip::clear_ssoft` using wrong address
- Fixed assignment in `mstatus` unit tests.
- Fixed address field for `mtvec`

## [v0.11.1] - 2024-02-15

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4 changes: 2 additions & 2 deletions riscv/src/register/mtvec.rs
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Expand Up @@ -23,7 +23,7 @@ impl Mtvec {
/// Returns the trap-vector base-address
#[inline]
pub fn address(&self) -> usize {
self.bits - (self.bits & 0b11)
self.bits >> 2
}

/// Returns the trap-vector mode
Expand All @@ -45,6 +45,6 @@ write_csr!(0x305);
/// Writes the CSR
#[inline]
pub unsafe fn write(addr: usize, mode: TrapMode) {
let bits = addr + mode as usize;
let bits = (addr << 2) | mode as usize;
_write(bits);
}
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