riscv: fix mtvec address field #225
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The `address` (BASE from the spec) needs to be 4-byte aligned, but the spec does not specify that the field is read/written as the masked address. Shifts the value in `mtvec::write(addr, mode)`, and `Mtvec::address` for a more intuitive API.
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This fails in QEMU, wish the spec was more explicit about how the |
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The
address(BASE from the spec) needs to be 4-byte aligned, but the spec does not specify that the field is read/written as the masked address.Shifts the value in
mtvec::write(addr, mode), andMtvec::addressfor a more intuitive API.