Spyglass clean up: multiple change to remove Spyglass warnings #2727
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W528: A signal or variable is set but never read
Spyglass would raise warning if default was not there even if all cases were described.
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core/issue_read_operands.sv
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| cvxif_off_instr_n = 32'b0; | ||
| for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin | ||
| if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin | ||
| case (issue_instr_i[i].fu) | ||
| CVXIF: begin | ||
| cvxif_valid_q[i] <= 1'b1; | ||
| cvxif_off_instr_q <= orig_instr[i]; | ||
| cvxif_valid_n[i] = 1'b1; | ||
| cvxif_off_instr_n = orig_instr[i]; | ||
| end | ||
| default: ; | ||
| endcase | ||
| end | ||
| end | ||
| if (flush_i) begin | ||
| cvxif_valid_q <= '0; | ||
| cvxif_off_instr_q <= 32'b0; | ||
| cvxif_valid_n = '0; | ||
| cvxif_off_instr_n = 32'b0; |
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| cvxif_off_instr_n = 32'b0; | |
| for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin | |
| if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin | |
| case (issue_instr_i[i].fu) | |
| CVXIF: begin | |
| cvxif_valid_q[i] <= 1'b1; | |
| cvxif_off_instr_q <= orig_instr[i]; | |
| cvxif_valid_n[i] = 1'b1; | |
| cvxif_off_instr_n = orig_instr[i]; | |
| end | |
| default: ; | |
| endcase | |
| end | |
| end | |
| if (flush_i) begin | |
| cvxif_valid_q <= '0; | |
| cvxif_off_instr_q <= 32'b0; | |
| cvxif_valid_n = '0; | |
| cvxif_off_instr_n = 32'b0; | |
| cvxif_off_instr_n = 32'b0; | |
| for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin | |
| if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin | |
| case (issue_instr_i[i].fu) | |
| CVXIF: begin | |
| cvxif_valid_n[i] = 1'b1; | |
| cvxif_off_instr_n = orig_instr[i]; | |
| end | |
| default: ; | |
| endcase |
| end | ||
| end |
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[verible-verilog-format] reported by reviewdog 🐶
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| end | |
| end | |
| if (flush_i) begin | |
| cvxif_valid_n = '0; | |
| cvxif_off_instr_n = 32'b0; | |
| end | |
| end |
| if (issue_instr_i[0].fu == CVXIF) begin | ||
| x_transaction_rejected_n = x_transaction_rejected; | ||
| end | ||
| end |
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| end | |
| end | |
| if (issue_instr_i[0].fu == CTRL_FLOW) begin | |
| pc_n = issue_instr_i[0].pc; | |
| is_compressed_instr_n = issue_instr_i[0].is_compressed; | |
| branch_predict_n = issue_instr_i[0].bp; | |
| end | |
| x_transaction_rejected_n = 1'b0; | |
| if (issue_instr_i[0].fu == CVXIF) begin | |
| x_transaction_rejected_n = x_transaction_rejected; | |
| end | |
| end |
| output logic cvxif_busy_o | ||
| ); | ||
| input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i | ||
| ); |
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| ); | |
| ); |
core/cva6_fifo_v3.sv
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| if (FPGA_ALTERA) | ||
| data_o = first_word_q ? data_ft_q : fifo_ram_rdata; | ||
| else | ||
| data_o = fifo_ram_rdata; |
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| if (FPGA_ALTERA) | |
| data_o = first_word_q ? data_ft_q : fifo_ram_rdata; | |
| else | |
| data_o = fifo_ram_rdata; | |
| if (FPGA_ALTERA) data_o = first_word_q ? data_ft_q : fifo_ram_rdata; | |
| else data_o = fifo_ram_rdata; |
core/cva6_fifo_v3.sv
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| if (FPGA_ALTERA) | ||
| data_o = first_word_q ? data_ft_q : fifo_ram_rdata; | ||
| else | ||
| data_o = fifo_ram_rdata; |
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| if (FPGA_ALTERA) | |
| data_o = first_word_q ? data_ft_q : fifo_ram_rdata; | |
| else | |
| data_o = fifo_ram_rdata; | |
| if (FPGA_ALTERA) data_o = first_word_q ? data_ft_q : fifo_ram_rdata; | |
| else data_o = fifo_ram_rdata; |
core/csr_regfile.sv
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| @@ -2508,16 +2509,14 @@ module csr_regfile | |||
| if (~rst_ni) begin | |||
| priv_lvl_q <= riscv::PRIV_LVL_M; | |||
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[verible-verilog-format] reported by reviewdog 🐶
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| priv_lvl_q <= riscv::PRIV_LVL_M; | |
| priv_lvl_q <= riscv::PRIV_LVL_M; |
core/csr_regfile.sv
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| @@ -2508,16 +2509,14 @@ module csr_regfile | |||
| if (~rst_ni) begin | |||
| priv_lvl_q <= riscv::PRIV_LVL_M; | |||
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| priv_lvl_q <= riscv::PRIV_LVL_M; | |
| priv_lvl_q <= riscv::PRIV_LVL_M; |
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Multiple changes to clean up code and remove Spyglass warnings.