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Spyglass clean up: multiple change to remove Spyglass warnings (#2727)
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Multiple changes to clean up code and remove Spyglass warnings.

Co-authored-by: JeanRochCoulon <[email protected]>
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@Gchauvon @JeanRochCoulon
Gchauvon and JeanRochCoulon authored Jan 23, 2025
1 parent 664c515 commit 3ce44b1
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Showing 16 changed files with 216 additions and 208 deletions.
2 changes: 1 addition & 1 deletion .gitlab-ci/expected_synth.yml
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@@ -1,2 +1,2 @@
cv32a65x:
gates: 185674
gates: 184701
1 change: 0 additions & 1 deletion core/branch_unit.sv
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Expand Up @@ -58,7 +58,6 @@ module branch_unit #(
// TODO(zarubaf): The ALU can be used to calculate the branch target
jump_base = (fu_data_i.operation == ariane_pkg::JALR) ? fu_data_i.operand_a[CVA6Cfg.VLEN-1:0] : pc_i;

target_address = {CVA6Cfg.VLEN{1'b0}};
resolve_branch_o = 1'b0;
resolved_branch_o.target_address = {CVA6Cfg.VLEN{1'b0}};
resolved_branch_o.is_taken = 1'b0;
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5 changes: 2 additions & 3 deletions core/commit_stage.sv
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Expand Up @@ -115,9 +115,8 @@ module commit_stage
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
commit_instr_i[i].op
)));
// Check if we issued a vector floating-point instruction to the accellerator
dirty_fp_state_o |= commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp;
// Check if we issued a vector floating-point instruction to the accellerator
))) | commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp;
end
end

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41 changes: 20 additions & 21 deletions core/csr_regfile.sv
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Expand Up @@ -886,7 +886,7 @@ module csr_regfile
// --------------------
cycle_d = cycle_q;
instret_d = instret_q;
if (!debug_mode_q) begin
if (!(CVA6Cfg.DebugEn && debug_mode_q)) begin
// increase instruction retired counter
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
if (commit_ack_i[i] && !ex_i.valid && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2])))
Expand Down Expand Up @@ -949,7 +949,7 @@ module csr_regfile
mcause_d = mcause_q;
mcounteren_d = mcounteren_q;
mscratch_d = mscratch_q;
mtval_d = mtval_q;
if (CVA6Cfg.TvalEn) mtval_d = mtval_q;
if (CVA6Cfg.RVH) begin
mtinst_d = mtinst_q;
mtval2_d = mtval2_q;
Expand Down Expand Up @@ -1720,9 +1720,10 @@ module csr_regfile
default: update_access_exception = 1'b1;
endcase
end

mstatus_d.sxl = riscv::XLEN_64;
mstatus_d.uxl = riscv::XLEN_64;
if (CVA6Cfg.IS_XLEN64) begin
mstatus_d.sxl = riscv::XLEN_64;
mstatus_d.uxl = riscv::XLEN_64;
end
if (!CVA6Cfg.RVU) begin
mstatus_d.mpp = riscv::PRIV_LVL_M;
end
Expand Down Expand Up @@ -2506,18 +2507,16 @@ module csr_regfile
// sequential process
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
priv_lvl_q <= riscv::PRIV_LVL_M;
priv_lvl_q <= riscv::PRIV_LVL_M;
// floating-point registers
fcsr_q <= '0;
fcsr_q <= '0;
// debug signals
debug_mode_q <= 1'b0;
if (CVA6Cfg.DebugEn) begin
dcsr_q <= '0;
dcsr_q.prv <= riscv::PRIV_LVL_M;
dcsr_q.xdebugver <= 4'h4;
dpc_q <= '0;
dscratch0_q <= {CVA6Cfg.XLEN{1'b0}};
dscratch1_q <= {CVA6Cfg.XLEN{1'b0}};
debug_mode_q <= 1'b0;
dcsr_q <= '{xdebugver: 4'h4, prv: riscv::PRIV_LVL_M, default: '0};
dpc_q <= '0;
dscratch0_q <= {CVA6Cfg.XLEN{1'b0}};
dscratch1_q <= {CVA6Cfg.XLEN{1'b0}};
end
// machine mode registers
mstatus_q <= 64'b0;
Expand All @@ -2530,12 +2529,12 @@ module csr_regfile
mcause_q <= {CVA6Cfg.XLEN{1'b0}};
mcounteren_q <= {CVA6Cfg.XLEN{1'b0}};
mscratch_q <= {CVA6Cfg.XLEN{1'b0}};
mtval_q <= {CVA6Cfg.XLEN{1'b0}};
fiom_q <= '0;
dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1};
icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1};
mcountinhibit_q <= '0;
acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator};
if (CVA6Cfg.TvalEn) mtval_q <= {CVA6Cfg.XLEN{1'b0}};
fiom_q <= '0;
dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1};
icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1};
mcountinhibit_q <= '0;
acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator};
// supervisor mode registers
if (CVA6Cfg.RVS) begin
medeleg_q <= {CVA6Cfg.XLEN{1'b0}};
Expand Down Expand Up @@ -2734,7 +2733,7 @@ module csr_regfile
assign rvfi_csr_o.mscratch_q = mscratch_q;
assign rvfi_csr_o.mepc_q = mepc_q;
assign rvfi_csr_o.mcause_q = mcause_q;
assign rvfi_csr_o.mtval_q = mtval_q;
assign rvfi_csr_o.mtval_q = CVA6Cfg.TvalEn ? mtval_q : '0;
assign rvfi_csr_o.fiom_q = fiom_q;
assign rvfi_csr_o.mcountinhibit_q = mcountinhibit_q;
assign rvfi_csr_o.cycle_q = cycle_q;
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19 changes: 12 additions & 7 deletions core/cva6_fifo_v3.sv
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Expand Up @@ -77,13 +77,18 @@ module cva6_fifo_v3 #(
read_pointer_n = read_pointer_q;
write_pointer_n = write_pointer_q;
status_cnt_n = status_cnt_q;
data_ft_n = data_ft_q;
first_word_n = first_word_q;
if (FPGA_EN && FPGA_ALTERA) data_ft_n = data_ft_q;
if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q;
if (FPGA_EN) begin
fifo_ram_we = '0;
fifo_ram_write_address = '0;
fifo_ram_wdata = '0;
data_o = (DEPTH == 0) ? data_i : (first_word_q ? data_ft_q : fifo_ram_rdata);
if (DEPTH == 0) begin
data_o = data_i;
end else begin
if (FPGA_ALTERA) data_o = first_word_q ? data_ft_q : fifo_ram_rdata;
else data_o = fifo_ram_rdata;
end
end else begin
data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q];
mem_n = mem_q;
Expand All @@ -96,7 +101,7 @@ module cva6_fifo_v3 #(
fifo_ram_we = 1'b1;
fifo_ram_write_address = write_pointer_q;
fifo_ram_wdata = data_i;
first_word_n = FPGA_ALTERA && first_word_q && pop_i;
if (FPGA_ALTERA) first_word_n = first_word_q && pop_i;
end else begin
// push the data onto the queue
mem_n[write_pointer_q] = data_i;
Expand All @@ -113,7 +118,7 @@ module cva6_fifo_v3 #(

if (pop_i && ~empty_o) begin
data_ft_n = data_i;
first_word_n = FPGA_EN && FPGA_ALTERA && first_word_q && push_i;
if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q && push_i;
// read from the queue is a default assignment
// but increment the read pointer...
if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0;
Expand Down Expand Up @@ -151,8 +156,8 @@ module cva6_fifo_v3 #(
read_pointer_q <= '0;
write_pointer_q <= '0;
status_cnt_q <= '0;
first_word_q <= '0;
data_ft_q <= '0;
if (FPGA_ALTERA) first_word_q <= '0;
if (FPGA_ALTERA) data_ft_q <= '0;
end else begin
if (flush_i) begin
read_pointer_q <= '0;
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6 changes: 2 additions & 4 deletions core/cvxif_issue_register_commit_if_driver.sv
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Expand Up @@ -36,16 +36,14 @@ module cvxif_issue_register_commit_if_driver #(
input logic [31:0] x_off_instr_i,
input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i,
input [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0][CVA6Cfg.XLEN-1:0] register_i,
input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i,
output logic cvxif_busy_o
input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i
);
// X_ISSUE_REGISTER_SPLIT = 0 : Issue and register transactions are synchrone
// Mandatory assignement
assign register_valid_o = issue_valid_o;
assign register_o.hartid = issue_req_o.hartid;
assign register_o.id = issue_req_o.id;
// cvxif can not take any more instruction if issue transaction is still up.
assign cvxif_busy_o = issue_valid_o && ~issue_ready_i;

always_comb begin
issue_valid_o = valid_i && ~flush_i;
issue_req_o.instr = x_off_instr_i;
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9 changes: 5 additions & 4 deletions core/decoder.sv
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Expand Up @@ -812,10 +812,11 @@ module decoder
unique case ({
CVA6Cfg.RVB, CVA6Cfg.RVZiCond
})
2'b00: illegal_instr = illegal_instr_non_bm;
2'b01: illegal_instr = illegal_instr_non_bm & illegal_instr_zic;
2'b10: illegal_instr = illegal_instr_non_bm & illegal_instr_bm;
2'b11: illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic;
2'b00: illegal_instr = illegal_instr_non_bm;
2'b01: illegal_instr = illegal_instr_non_bm & illegal_instr_zic;
2'b10: illegal_instr = illegal_instr_non_bm & illegal_instr_bm;
2'b11: illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic;
default: ; // TODO: Check that default case is not synthesized.
endcase
end
end
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2 changes: 1 addition & 1 deletion core/frontend/frontend.sv
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Expand Up @@ -240,7 +240,7 @@ module frontend
4'b0001: begin
ras_pop = 1'b0;
ras_push = 1'b0;
if (CVA6Cfg.BTBEntries && btb_prediction_shifted[i].valid) begin
if (CVA6Cfg.BTBEntries != 0 && btb_prediction_shifted[i].valid) begin
predict_address = btb_prediction_shifted[i].target_address;
cf_type[i] = ariane_pkg::JumpR;
end
Expand Down
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