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Merge branch 'master' of https://github.com/mitchgu/GuitarHeroFFE
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Ryan Berg committed Dec 6, 2015
2 parents 8039062 + a8544db commit 2af5c0c
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58 changes: 58 additions & 0 deletions Nexys4Guitar/src/hdl/calculate_norm.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/04/2015 12:43:02 AM
// Design Name:
// Module Name: calculate_norm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module calculate_norm(
input clk,
input [31:0] mag_squared_tdata,
input mag_squared_tlast,
input [11:0] mag_squared_tuser,
input mag_squared_tvalid,
output [20:0] norm_tdata,
output norm_tvalid
);

wire in_range;
assign in_range = ~|mag_squared_tuser[11:10];

reg [47:0] accumulator_tdata = 0;
reg accumulator_tvalid;
always @(posedge clk) begin
if (mag_squared_tlast) accumulator_tvalid <= 1;
else if (accumulator_tvalid) begin
accumulator_tvalid <= 0;
accumulator_tdata <= 0;
end
if (in_range & mag_squared_tvalid & (mag_squared_tuser[9:0] > 72))
accumulator_tdata <= accumulator_tdata + mag_squared_tdata;
end

wire [23:0] norm_out;
norm_sqrt normer (
.aclk(clk), // input wire aclk
.s_axis_cartesian_tvalid(accumulator_tvalid), // input wire s_axis_cartesian_tvalid
.s_axis_cartesian_tdata(accumulator_tdata), // input wire [47 : 0] s_axis_cartesian_tdata
.m_axis_dout_tvalid(norm_tvalid), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(norm_out) // output wire [23 : 0] m_axis_dout_tdata
);
assign norm_tdata = norm_out[20:0];

endmodule
107 changes: 107 additions & 0 deletions Nexys4Guitar/src/hdl/correlator.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/18/2015 02:16:55 AM
// Design Name:
// Module Name: process_fft
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module correlator(
input clk,
input [15:0] magnitude_tdata,
input magnitude_tlast,
input [11:0] magnitude_tuser,
input magnitude_tvalid,
input [20:0] norm_tdata,
input norm_tvalid,
output reg [41:0] dot_product,
output reg [31:0] normalizer,
output reg dot_product_valid,
output [76:0] debug
);

parameter REF_MIF = "../mif/00.mif";
parameter NORM_REF = 21'd0;

wire in_range;
assign in_range = ~|magnitude_tuser[11:10];

wire less_than_72;
assign less_than_72 = (magnitude_tuser[9:0] < 72);

// Inferred bram
reg [15:0] ref_mag [0:1023];
initial $readmemb(REF_MIF, ref_mag);

reg dot_ce, dot_clr, dot_sel;
wire [15:0] dot_a;
wire [15:0] dot_b;
wire [47:0] dot_p;
reg [15:0] norm_a;
reg [15:0] mag_a;
reg [15:0] ref_a;
wire [15:0] norm_round;
assign norm_round = (NORM_REF + 5'b10000) >> 5;
assign dot_a = (dot_sel) ? norm_a : mag_a;
assign dot_b = (dot_sel) ? norm_round : ref_a;
dot_product dotter (
.CLK(clk), // input wire CLK
.CE(dot_ce), // input wire CE
.SCLR(dot_clr), // input wire SCLR
.SEL(dot_sel),
.A(dot_a), // input wire [15 : 0] A
.B(dot_b), // input wire [15 : 0] B
.P(dot_p) // output wire [41 : 0] P
);

reg [4:0] dot_product_timer = 0;
reg [5:0] normalizer_timer = 0;
always @(posedge clk) begin
mag_a <= less_than_72 ? 16'b0 : magnitude_tdata;
ref_a <= less_than_72 ? 16'b0 : ref_mag[magnitude_tuser[9:0]];

dot_product_timer <= {dot_product_timer[3:0], 1'b0};
normalizer_timer <= {normalizer_timer[4:0], 1'b0};

if (magnitude_tvalid) begin
dot_ce <= in_range;
end
if (magnitude_tlast) begin
dot_product_timer[0] <= 1;
dot_ce <= 1;
end
if (dot_product_timer[4]) dot_product <= dot_p[41:0];
if (norm_tvalid) begin
norm_a <= (norm_tdata + 5'b10000)>>5;
dot_sel <= 1;
dot_ce <= 1;
normalizer_timer[0] <= 1;
end
if (normalizer_timer[4]) begin
normalizer <= dot_p[31:0];
dot_product_valid <= 1;
dot_sel <= 0;
dot_ce <= 0;
dot_clr <= 1;
end
else if (normalizer_timer[5]) begin
dot_product_valid <= 0;
dot_clr <= 0;
end
end
assign debug = {dot_a,dot_b,dot_p,dot_ce,dot_sel,dot_clr};

endmodule
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