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Merge branch 'master' of github.com:mitchgu/GuitarHeroFFE
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mitchgu committed Dec 6, 2015
2 parents 13f1342 + f974013 commit a8544db
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Showing 5 changed files with 166 additions and 1 deletion.
43 changes: 43 additions & 0 deletions Nexys4Game/src/hdl/AV_block.v
Original file line number Diff line number Diff line change
@@ -1,8 +1,51 @@
module AV_block(
input clk,
input clk65,
input pause,

output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS


);

wire [10:0] hcount;
wire [9:0] vcount;

wire [12:0] menu_pixel;

xvga xvga(
.vclock(clk65),
.hcount(hcount),
.vcount(vcount),
.vsync(VGA_VS),
.hsync(VGA_HS),
.blank(),
);

AV_integrator integrator(
.clk65(clk65),
.menu_pixel(menu_pixel),
.score_pixel(),
.string1_pixel(),
.string2_pixel(),
.string3_pixel(),
.string4_pixel(),
.string5_pixel(),
.string6_pixel(),
.bg_pixel(),
.pixel( {VGA_R, VGA_G, VGA_B} )
);

AV_menu_graphics menu(
.clk65(clk65),
.pause(pause),
.hcount(hcount),
.vcount(vcount),
.menu_pixel(menu_pixel)
);

endmodule
50 changes: 50 additions & 0 deletions Nexys4Game/src/hdl/AV_integrator.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
module AV_integrator(
input clk65,

input [12:0] menu_pixel,
input [12:0] score_pixel,
input [12:0] string1_pixel, //MSB is whether or not to use the pixel
input [12:0] string2_pixel,
input [12:0] string3_pixel,
input [12:0] string4_pixel,
input [12:0] string5_pixel,
input [12:0] string6_pixel,

input [11:0] bg_pixel,

output reg [11:0] pixel


);

always @(posedge clk65) begin //maybe make this assign and wires instead?

if( menu_pixel[12] == 1'b1 ) begin
pixel <= menu_pixel[11:0];
end
else if( score_pixel[12] == 1'b1 ) begin
pixel <= score_pixel[11:0];
end
else if( string1_pixel[12] == 1'b1 ) begin
pixel <= string1_pixel[11:0];
end
else if( string2_pixel[12] == 1'b1 ) begin
pixel <= string2_pixel[11:0];
end
else if( string3_pixel[12] == 1'b1 ) begin
pixel <= string3_pixel[11:0];
end
else if( string4_pixel[12] == 1'b1 ) begin
pixel <= string4_pixel[11:0];
end
else if( string5_pixel[12] == 1'b1 ) begin
pixel <= string5_pixel[11:0];
end
else if( string6_pixel[12] == 1'b1 ) begin
pixel <= string6_pixel[11:0];
end
else pixel <= bg_pixel[11:0];

end

endmodule
25 changes: 25 additions & 0 deletions Nexys4Game/src/hdl/AV_menu_graphics.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
module AV_menu_graphics(
input clk65,
input pause,
input [10:0] hcount,
input [9:0] vcount,

output [12:0] menu_pixel
);

localparam WIDTH = 800;
localparam HEIGHT = 600;
localparam COLOR = 12'hD_D_D;
localparam startX = 100;
localparam startY = 50;


always @(posedge clk65) begin
if( hcount >= startX && hcount < (startX + WIDTH) &&
vcount >= startY && vcount < (startY + HEIGHT))
menu_pixel = {pause, COLOR};
else menu_pixel = 0;

end

endmodule
11 changes: 10 additions & 1 deletion Nexys4Game/src/hdl/nexys4_game.v
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,9 @@ module nexys4_game(
wire CLK25MHZ;
clock_4divider clk_divider(.clk(CLK100MHZ),.clk_div(CLK25MHZ));

wire CLK65MHZ;
clk_wiz_65 clk_65(.clk_in(CLK100MHZ),.clk_out(CLK_65MHZ));

// INSTANTIATE SEVEN SEGMENT DISPLAY
wire [31:0] seg_data;
wire [6:0] segments;
Expand Down Expand Up @@ -108,7 +111,13 @@ module nexys4_game(
);

AV_block AV(

.clk(CLK100MHZ),
.clk65(CLK65MHZ),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS)



Expand Down
38 changes: 38 additions & 0 deletions Nexys4Game/src/hdl/xvga.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
module xvga(input vclock,
output reg [10:0] hcount, // pixel number on current line
output reg [9:0] vcount, // line number
output reg vsync,hsync,blank);

// horizontal: 1344 pixels total
// display 1024 pixels per line
reg hblank,vblank;
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = (hcount == 1023);
assign hsyncon = (hcount == 1047);
assign hsyncoff = (hcount == 1183);
assign hreset = (hcount == 1343);

// vertical: 806 lines total
// display 768 lines
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == 767);
assign vsyncon = hreset & (vcount == 776);
assign vsyncoff = hreset & (vcount == 782);
assign vreset = hreset & (vcount == 805);

// sync and blanking
wire next_hblank,next_vblank;
assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank;
assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank;
always @(posedge vclock) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low

vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low

blank <= next_vblank | (next_hblank & ~hreset);
end
endmodule

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