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14 Open 71 Closed
14 Open 71 Closed
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Issues list

Incorrect comments in the FMC ADCs SPI interface
#110 opened Oct 24, 2024 by augustofg
[MONIT1/MONIT tag delay] delays are applied as "ADC clock cycles" granularity bug
#81 opened Jul 8, 2020 by lerwys
@lerwys
[FOFB sync] FOFB sync only works when switching is in "switching" mode bug
#80 opened Jul 8, 2020 by lerwys
@lerwys
[wb_fmcpico1m_4ch] Aquisition clock must be synchonized with machine clock bug
#79 opened Jun 26, 2020 by lerwys
@lerwys
Allow simulataneous range selection on XBPM gateware enhancement
#78 opened Jun 10, 2020 by danielot
@lerwys
[wb_trigger] Add enable input in each logical trigger enhancement
#74 opened Aug 18, 2018 by danielot
[acq_core] More options for data-driven trigger enhancement
#71 opened Jul 13, 2017 by danielot
[wb_trigger_iface] Missing pulse extender check if length = 0 bug
#69 opened Jun 23, 2017 by lerwys
[flash_loader] Implement Flash Loader via PCIe/Wishbone enhancement
#55 opened Apr 27, 2016 by lerwys
[fmc130m] Top .ucf .xdc files for FMC130M are misleading
#53 opened Feb 19, 2016 by lerwys
[vivado_project] AXI Interconnect BPM is not generated as VHDL and simulation fails bug
#51 opened Dec 18, 2015 by lerwys
[pcie_core] Cannot access DDR data from high address bug
#45 opened Jun 12, 2015 by lerwys
2
[wb_acq_core] Check lmt_curr_chan_id signal and its use bug
#43 opened Mar 25, 2015 by lerwys
[wb_fmc130m_4ch] ADC clock current delay value not used
#39 opened Oct 14, 2014 by lerwys
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