DMA cast support and new HW FIFO interface

.github/workflows/sim-apps-job/test_apps.py

@@ -33,6 +33,7 @@ class BColors:
     "example_spi_read",
     "example_spidma_powergate",
     "example_spi_write",
+    "example_dma_subaddressing",
 ]
 
 app_list = [app for app in os.listdir("sw/applications")]

core-v-mini-mcu.core

@@ -339,6 +339,7 @@ targets:
         vsim_options:
         - -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi
         - -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs
+        - -voptargs=+acc=npr
       vcs:
         vcs_options:
          - -override_timescale=1ns/1ps

docs/source/Peripherals/DMA.md

@@ -318,6 +318,8 @@ The previous parameters, including the register offsets, can be found at `sw/dev
     - 0: _linear mode_
     - 1: _circular mode_
     - 2: _address mode_
+    - 3: _subaddress mode_
+    - 4: _hardware fifo mode_
 
 <hr>
 
@@ -560,7 +562,7 @@ If senseless configurations are input to functions, assertions may halt the whol
 
 #### Transaction modes
 
-There are three different transaction modes:
+There are five different transaction modes:
 
 **Single Mode:** The default mode, where the DMA channel will perform the copy from the source target to the destination, and trigger an interrupt once done.
 
@@ -569,6 +571,10 @@ There are three different transaction modes:
 **Address Mode:** Instead of using the destination pointer and increment to decide where to copy information, an _address list_ must be provided, containing addresses for each data unit being copied. It is only carried out in _single_ mode. 
 In this mode it's possible to perform only 1D transactions.
 
+**Subaddress Mode:** In this mode, the DMA can be configured to transfer words, half words or bytes from a slot (e.g. SPI) or whichever fixed location to another destination target one. This mode is mostly useful when, in case of fixed source target, the source data type is a half word or a byte. This mode allows the DMA to sequentially read the half words or bytes composing the word retrieved from the slot (or fixed location), and to forward them to the destination target.
+
+**Hardware Fifo Mode:** the DMA fetches data from the source target and forwards it directly to an external accelerator tightly coupled with the DMA itself. The accelerator must have two internal fifos. The first one, referred to as hardware read fifo, is filled with source target data directly from the DMA. Then, the accelerator is in charge of popping from the hardware read fifo and processing the data. In the end, the results must be pushed into another fifo, referred to as hardware write fifo. The DMA reads data from the hardware write fifo and store it into the destination target.
+
 
 
 #### Windows
@@ -747,8 +753,9 @@ Here is a brief overview of the examples:
 6) Matrix zero padding
 7) Multichannel mem2mem transaction, focusing on the IRQ handler
 8) Multichannel flash2mem transaction using the SPI FLASH
+9) Single-channel flash2mem transactions with different data widths (bytes, half-words and words) using the SPI FLASH
 
-The complete code for these examples can be found in `sw/applications/example_dma`, `sw/applications/example_dma_2d`, `sw/applications/example_dma_multichannel` and `sw/applications/example_dma_sdk`. These applications offer both verification and performance estimation modes, enabling users to verify the DMA and measure the application's execution time.
+The complete code for these examples can be found in `sw/applications/example_dma`, `sw/applications/example_dma_2d`, `sw/applications/example_dma_multichannel`, `sw/applications/example_dma_sdk` and `sw/applications/example_dma_subaddressing`. These applications offer both verification and performance estimation modes, enabling users to verify the DMA and measure the application's execution time.
 
 The user is strongly incouraged to look at these applications, as well as any other application that employs the DMA, to gain insight in practical examples of the use of this peripheral. Some aspects or specific usecases might in fact not be present in this guide and could be found in the applications.
 

hw/core-v-mini-mcu/ao_peripheral_subsystem.sv

@@ -6,6 +6,7 @@ module ao_peripheral_subsystem
   import obi_pkg::*;
   import reg_pkg::*;
   import power_manager_pkg::*;
+  import hw_fifo_pkg::*;
 #(
     parameter AO_SPC_NUM = 0,
     //do not touch these parameters
@@ -76,6 +77,9 @@ module ao_peripheral_subsystem
     output logic                                                      dma_done_intr_o,
     output logic                                                      dma_window_intr_o,
 
+    output hw_fifo_req_t  [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] hw_fifo_req_o,
+    input  hw_fifo_resp_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] hw_fifo_resp_i,
+
     // External PADs
     output reg_req_t pad_req_o,
     input  reg_rsp_t pad_resp_i,
@@ -395,6 +399,8 @@ module ao_peripheral_subsystem
       .reg_rsp_t(reg_pkg::reg_rsp_t),
       .obi_req_t(obi_pkg::obi_req_t),
       .obi_resp_t(obi_pkg::obi_resp_t),
+      .hw_fifo_req_t(hw_fifo_pkg::hw_fifo_req_t),
+      .hw_fifo_resp_t(hw_fifo_pkg::hw_fifo_resp_t),
       .GLOBAL_SLOT_NUM(DMA_GLOBAL_TRIGGER_SLOT_NUM),
       .EXT_SLOT_NUM(DMA_EXT_TRIGGER_SLOT_NUM)
   ) dma_subsystem_i (
@@ -409,6 +415,8 @@ module ao_peripheral_subsystem
       .dma_write_resp_i,
       .dma_addr_req_o,
       .dma_addr_resp_i,
+      .hw_fifo_req_o,
+      .hw_fifo_resp_i,
       .global_trigger_slot_i(dma_global_trigger_slots),
       .ext_trigger_slot_i(dma_ext_trigger_slots),
       .ext_dma_stop_i(ext_dma_stop_i),

hw/core-v-mini-mcu/core_v_mini_mcu.sv

@@ -5,6 +5,7 @@
 module core_v_mini_mcu
   import obi_pkg::*;
   import reg_pkg::*;
+  import hw_fifo_pkg::*;
 #(
     parameter COREV_PULP = 0,
     parameter FPU = 0,
@@ -304,6 +305,9 @@ module core_v_mini_mcu
     output obi_req_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_req_o,
     input obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_resp_i,
 
+    output hw_fifo_req_t  [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] hw_fifo_req_o,
+    input  hw_fifo_resp_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] hw_fifo_resp_i,
+
     input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
 
     output reg_req_t ext_peripheral_slave_req_o,
@@ -665,6 +669,8 @@ module core_v_mini_mcu
       .dma_addr_resp_i(dma_addr_resp),
       .dma_done_intr_o(dma_done_intr),
       .dma_window_intr_o(dma_window_intr),
+      .hw_fifo_req_o,
+      .hw_fifo_resp_i,
       .spi_flash_intr_event_o(spi_flash_intr),
       .pad_req_o,
       .pad_resp_i,

hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl

@@ -5,6 +5,7 @@
 module core_v_mini_mcu
   import obi_pkg::*;
   import reg_pkg::*;
+  import hw_fifo_pkg::*;
 #(
     parameter COREV_PULP = 0,
     parameter FPU = 0,
@@ -58,6 +59,9 @@ ${pad.core_v_mini_mcu_interface}
     output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_req_o,
     input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_resp_i,
 
+    output hw_fifo_req_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] hw_fifo_req_o,
+    input hw_fifo_resp_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] hw_fifo_resp_i,
+
     input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
 
     output reg_req_t ext_peripheral_slave_req_o,
@@ -413,6 +417,8 @@ ${pad.core_v_mini_mcu_interface}
       .dma_addr_resp_i(dma_addr_resp),
       .dma_done_intr_o(dma_done_intr),
       .dma_window_intr_o(dma_window_intr),
+      .hw_fifo_req_o,
+      .hw_fifo_resp_i,
       .spi_flash_intr_event_o(spi_flash_intr),
       .pad_req_o,
       .pad_resp_i,

hw/core-v-mini-mcu/include/hw_fifo_pkg.sv

@@ -0,0 +1,20 @@
+// Copyright 2022 OpenHW Group
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+package hw_fifo_pkg;
+
+  typedef struct packed {
+    logic pop;
+    logic push;
+    logic [31:0] data;
+  } hw_fifo_req_t;
+
+  typedef struct packed {
+    logic empty;
+    logic full;
+    logic push;
+    logic [31:0] data;
+  } hw_fifo_resp_t;
+
+endpackage

hw/core-v-mini-mcu/include/x-heep_packages.core

@@ -14,6 +14,7 @@ filesets:
     - obi_pkg.sv
     - reg_pkg.sv
     - power_manager_pkg.sv
+    - hw_fifo_pkg.sv
     - core_v_mini_mcu_pkg.sv
     file_type: systemVerilogSource
 

hw/ip/dma/data/dma.hjson

@@ -186,12 +186,14 @@
       hwaccess: "hro",
       resval:        0,
       fields: [
-        { bits: "1:0", name: "MODE",
+        { bits: "2:0", name: "MODE",
           desc: "DMA operation mode",
           enum: [
             { value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"},
             { value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"},
-            { value: "2", name: "ADDRESS_MODE" , desc: "Transfers data using as destination address the data from ADD_PTR"},
+            { value: "2", name: "ADDRESS_MODE", desc: "Transfers data using as destination address the data from ADD_PTR"},
+            { value: "3", name: "SUBADDRESS_MODE", desc: "Implements transferring of data when SRC_PTR is fixed and related to a peripheral"},
+            { value: "4", name: "HW_FIFO_MODE", desc: "Mode for exploting external stream accelerators"}
           ]
         }
       ]
@@ -302,6 +304,23 @@
       fields: [
         { bits: "0", name: "FLAG", desc: "Set for window done interrupt" }
       ]
-    }
+    },
+    { name:     "HW_FIFO_MODE_SIGN_EXT",
+      desc:     '''In HW_FIFO_MODE, is the input data to be sign extended before sending it to the hw read fifo?
+                    (The input of the hw read fifo is on 32 bits, which could be wider than the src data type)''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:        0,
+
+      fields: [
+        { bits: "0", name: "HW_FIFO_SIGNED", 
+          desc: "Extend the sign to 32 bits",
+          enum: [
+            { value: "0", name: "NO_EXTEND", desc: "Does not extend the sign"},
+            { value: "1", name: "EXTEND", desc: "Extends the sign"},
+          ]
+        }
+      ]
+    },
   ]
 }

hw/ip/dma/dma.core

@@ -18,6 +18,8 @@ filesets:
     - rtl/dma_obiread_fsm.sv
     - rtl/dma_obiread_addr_fsm.sv
     - rtl/dma_obiwrite_fsm.sv
+    - rtl/hw_r_fifo_ctrl.sv
+    - rtl/hw_w_fifo_ctrl.sv
     - rtl/dma.sv
     file_type: systemVerilogSource