Add GL verification to uart

efabless · Apr 2, 2024 · a57f93a · a57f93a
1 parent 1cdd84d
commit a57f93a
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Showing 3 changed files with 17 additions and 2 deletions.
diff --git a/hdl/rtl/EF_UART.v b/hdl/rtl/EF_UART.v
@@ -87,8 +87,8 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
     output  wire            tx
 );
 
-    wire        tx_done;
-    wire        rx_done;
+    (* keep *) wire        tx_done;
+    (* keep *) wire        rx_done;
 
     wire        b_tick;
 

diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
@@ -10,11 +10,21 @@ RTL_MACROS += ""
 BUS_TYPE ?= APB
 ifeq ($(BUS_TYPE),APB)
     RTL_MACROS += -DBUS_TYPE_APB
+    DESIGN_NAME = EF_UART_APB
 else ifeq ($(BUS_TYPE),AHB)
     RTL_MACROS += -DBUS_TYPE_AHB
+    DESIGN_NAME = EF_UART_AHBL
 else ifeq ($(BUS_TYPE),WISHBONE)
     RTL_MACROS += -DBUS_TYPE_WISHBONE
+    DESIGN_NAME = EF_UART_wb
 endif
+## netlist Gen 
+GL_MACROS += -DGL -DFUNCTIONAL  $(RTL_MACROS) -DUNIT_DELAY=\#1 
+PRE_SYS_FILES = $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
+PDK_DIR = $(HOME)/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/
+PDK_FILES = $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v # get this from openlane logs in the future 
+POST_SYS_FILES = $(PWD)/top.v $(VIP_FILES) $(PWD)/../../hdl/gl/synthesis/nl/$(DESIGN_NAME).nl.v
+
 # RTL_MACROS ?= "-DSKIP_WAVE_DUMP"
 YAML_FILE = $(PWD)/../../EF_UART.yaml
 MAKEFLAGS += --no-print-directory

diff --git a/verify/uvm-python/top.v b/verify/uvm-python/top.v
@@ -38,8 +38,13 @@ module top();
         EF_UART_wb dut(.rx(RX), .tx(TX), .clk_i(CLK), .rst_i(~rst_i), .adr_i(adr_i), .dat_i(dat_i), .dat_o(dat_o), .sel_i(sel_i), .cyc_i(cyc_i), .stb_i(stb_i), .ack_o(ack_o),.we_i(we_i), .irq(irq));
     `endif // BUS_TYPE_WISHBONE
     // monitor inside signals
+`ifndef GL 
     wire tx_done = dut.instance_to_wrap.tx_done;
     wire rx_done = dut.instance_to_wrap.rx_done;
+`else 
+    wire tx_done = dut.\instance_to_wrap.tx_done ;
+    wire rx_done = dut.\instance_to_wrap.rx_done ;
+`endif // GL
     `ifndef SKIP_WAVE_DUMP
         initial begin
             $dumpfile ({"waves.vcd"});