Fix: WFI didn't manage returns from IDLE properly if mie=0. enchance

test1.S to better cover WFI.
dpretet · Nov 1, 2023 · 9e59b70 · 9e59b70
1 parent 55f625b
commit 9e59b70
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Showing 14 changed files with 187 additions and 106 deletions.
diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
@@ -826,9 +826,12 @@ module friscv_control
                                     `endif
                                     status[4] <= 1'b1;
                                     flush_pipe <= 1'b1;
-                                    pc_reg <= mtvec;
+                                    if (sb_mie)
+                                        pc_reg <= mtvec;
                                     arvalid <= 1'b0;
                                     cfsm <= WFI;
+                                end else begin
+                                    pc_reg <= pc;
                                 end
 
                             // CSR instructions
@@ -892,10 +895,16 @@ module friscv_control
                         `endif
                         status <= 5'b0;
                         flush_pipe <= 1'b1;
-                        if (USER_MODE) priv_mode <= `MMODE;
-                        arid <= next_id(arid, MAX_ID, AXI_ID_MASK);
-                        araddr <= mtvec;
-                        pc_reg <= mtvec;
+                        if (USER_MODE && sb_mie) priv_mode <= `MMODE;
+
+                        if (sb_mie) begin
+                            arid <= next_id(arid, MAX_ID, AXI_ID_MASK);
+                            araddr <= mtvec;
+                            pc_reg <= mtvec;
+                        end else begin
+                            araddr <= pc;
+                            pc_reg <= pc;
+                        end
                         arvalid <= 1'b1;
                         cfsm <= FETCH;
                     end
@@ -1200,7 +1209,7 @@ module friscv_control
                 wfi_tw <= 1'b0;
             end else begin
 
-                if (cfsm==WFI && priv_mode!=`MMODE) begin
+                if (cfsm==WFI && priv_mode!=`MMODE && sb_mie) begin
                     tw <= tw + 1'b1;
                 end else begin
                     tw <= '0;

diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed Nov  1 17:02:29 2023
+[*] Wed Nov  1 17:32:10 2023
 [*]
 [dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd"
-[dumpfile_mtime] "Wed Nov  1 17:00:10 2023"
-[dumpfile_size] 224490635
+[dumpfile_mtime] "Wed Nov  1 17:03:56 2023"
+[dumpfile_size] 9007697
 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw"
-[timestart] 6064
+[timestart] 6058
 [size] 2560 1440
 [pos] -1 -1
-*-5.355745 6248 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-5.355745 6239 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.
@@ -25,7 +25,7 @@
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.
 [sst_width] 365
-[signals_width] 334
+[signals_width] 344
 [sst_expanded] 1
 [sst_vpaned_height] 365
 @c00200
@@ -288,7 +288,9 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_valid
 -
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring
+@29
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.async_trap_occuring
+@28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sync_trap_occuring
 @200
 -
@@ -610,9 +612,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKER
 -Region 1
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_cfg[7:0]
-@23
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_addr[31:0]
-@22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_base[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_mask[31:0]
 @1000200

diff --git a/test/priv_sec_testsuite/README.md b/test/priv_sec_testsuite/README.md
@@ -18,3 +18,7 @@ instructions or tries to access CSR registers reserved to m-mode
 
 Generate interrupts and manage them. Check U-mode move back M-mode to handle the interrupt. Check
 WFI is correctly supported by U-mode.
+
+## Test 2: Check PMP Regions
+
+Checks the three memory region types and tries access across the region and out of its boundaries
diff --git a/test/priv_sec_testsuite/tests/env/pmp_service.S b/test/priv_sec_testsuite/tests/env/pmp_service.S
@@ -201,8 +201,8 @@ CHECK_RW_PMP:
 ////////////////////////////////////////////
 INTP_SERVICE:
     # Enable IRQ
-    lui t5, %hi(MIE_ON)
-    addi t5, t5, %lo(MIE_ON)
+    lui t5, %hi(MPIE_ON)
+    addi t5, t5, %lo(MPIE_ON)
     csrr t4, mstatus
     or t4, t4, t5
     csrw mstatus, t4

diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test1.v b/test/priv_sec_testsuite/tests/rv32ui-p-test1.v
@@ -1,9 +1,9 @@
 @00010000
 6F 00 80 08 73 2F 20 34 93 0E 80 00 63 0A DF 1B
-93 0E 90 00 63 02 DF 1B 93 0E B0 00 63 02 DF 1F
-93 0E 20 00 63 00 DF 1F B7 0E 00 80 93 8E BE 00
-63 04 DF 1F B7 0E 00 80 93 8E 3E 00 63 0E DF 1D
-B7 0E 00 80 93 8E 7E 00 63 08 DF 1D 93 0E 50 00
+93 0E 90 00 63 02 DF 1B 93 0E B0 00 63 04 DF 23
+93 0E 20 00 63 02 DF 23 B7 0E 00 80 93 8E BE 00
+63 06 DF 23 B7 0E 00 80 93 8E 3E 00 63 00 DF 23
+B7 0E 00 80 93 8E 7E 00 63 0A DF 21 93 0E 50 00
 63 04 DF 17 93 0E 70 00 63 00 DF 17 93 0E 10 00
 63 0C DF 15 13 0F 00 00 63 04 0F 00 67 00 0F 00
 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53
@@ -26,21 +26,29 @@ B7 0E 00 80 93 8E 7E 00 63 08 DF 1D 93 0E 50 00
 73 00 10 00 93 02 00 00 63 8A 02 00 73 90 52 10
 B7 B2 00 00 93 82 92 10 73 90 22 30 73 50 00 30
 97 02 00 00 93 82 42 01 73 90 12 34 73 25 40 F1
-73 00 20 30 6F 00 C0 06 93 8F 1F 00 73 00 10 00
-93 0E 90 00 63 96 D8 03 37 0F 00 00 13 0F 0F 08
+73 00 20 30 6F 00 00 0B 93 8F 1F 00 73 00 10 00
+93 0E 70 00 63 8C 1E 05 93 0E 80 00 63 8C 1E 03
+93 0E 90 00 63 90 D8 07 37 0F 00 00 13 0F 0F 08
 F3 2E 00 30 B3 EE EE 01 73 90 0E 30 37 1F 00 00
 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01 73 90 4E 30
-F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30
-73 00 10 00 13 0A 1A 00 F3 2E 10 34 93 8E 4E 00
-73 90 1E 34 73 00 20 30 13 0A 1A 00 73 00 20 30
-93 08 90 00 73 00 00 00 93 02 00 00 13 03 00 00
-93 03 40 06 93 82 12 00 23 20 50 00 03 23 00 00
-E3 9A 72 FE 63 9E 62 00 13 0A 00 00 13 03 10 00
-73 00 50 10 63 16 6A 00 6F 00 C0 02 63 14 30 02
-0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00
-93 08 D0 05 13 85 01 00 93 8F 1F 00 73 00 10 00
-73 00 10 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05
-13 05 00 00 73 00 10 00 73 00 10 00 73 10 00 C0
+6F 00 40 03 37 0F 00 00 13 0F FF F7 F3 2E 00 30
+B3 FE EE 01 73 90 0E 30 6F 00 C0 01 37 FF FF FF
+13 0F FF 7F F3 2E 40 30 B3 FE EE 01 73 90 4E 30
+6F 00 40 00 F3 2E 10 34 93 8E 4E 00 73 90 1E 34
+73 00 20 30 73 00 10 00 13 0A 1A 00 F3 2E 10 34
+93 8E 4E 00 73 90 1E 34 73 00 20 30 13 0A 1A 00
+73 00 20 30 93 08 90 00 73 00 00 00 93 02 00 00
+13 03 00 00 93 03 40 06 93 82 12 00 23 20 50 00
+03 23 00 00 E3 9A 72 FE 63 92 62 04 13 0A 00 00
+13 03 10 00 73 00 50 10 63 1A 6A 02 93 08 80 00
+73 00 00 00 73 00 50 10 93 08 70 00 73 00 00 00
+13 00 00 00 73 00 50 10 13 00 00 00 73 00 50 10
+13 00 00 00 6F 00 C0 02 63 14 30 02 0F 00 F0 0F
+63 80 01 00 93 91 11 00 93 E1 11 00 93 08 D0 05
+13 85 01 00 93 8F 1F 00 73 00 10 00 73 00 10 00
+0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00
+73 00 10 00 73 00 10 00 73 10 00 C0 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00
 @00011000

diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v
@@ -111,7 +111,7 @@ B7 7E 77 77 93 8E 7E 77 73 90 2E 3A 73 2F 20 3A
 63 84 EE 01 6F E0 0F 92 73 10 20 3A B7 7E 77 77
 93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 84 EE 01
 6F E0 4F 90 73 10 30 3A 6F 00 40 2E 37 0F 00 00
-13 0F 8F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30
+13 0F 0F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30
 37 1F 00 00 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01
 73 90 4E 30 6F 00 80 2B 13 04 14 00 73 00 20 30
 13 06 F6 FF 13 56 36 00 93 D5 25 00 B3 E5 C5 00

diff --git a/test/priv_sec_testsuite/tests/rv32ui-v-test1.v b/test/priv_sec_testsuite/tests/rv32ui-v-test1.v
@@ -121,11 +121,11 @@ E3 9C 07 FD 73 90 08 10 93 97 26 00 B3 06 F6 00
 63 94 E5 04 93 96 26 00 B3 06 D6 00 23 A0 F6 00
 73 00 05 12 83 20 C1 00 13 01 01 01 67 80 00 00
 93 E7 07 04 6F F0 1F FE 97 47 00 00 23 A4 07 AC
-6F F0 1F F0 17 05 00 00 13 05 85 56 EF F0 5F D0
-13 05 30 00 EF F0 5F D6 17 05 00 00 13 05 85 59
+6F F0 1F F0 17 05 00 00 13 05 45 5D EF F0 5F D0
+13 05 30 00 EF F0 5F D6 17 05 00 00 13 05 45 60
 EF F0 1F CF 13 05 30 00 EF F0 1F D5 17 05 00 00
-13 05 C5 5C EF F0 DF CD 13 05 30 00 EF F0 DF D3
-17 05 00 00 13 05 05 5D EF F0 9F CC 13 05 30 00
+13 05 85 63 EF F0 DF CD 13 05 30 00 EF F0 DF D3
+17 05 00 00 13 05 C5 63 EF F0 9F CC 13 05 30 00
 EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04
 23 26 11 04 23 22 91 04 23 20 21 05 23 2E 31 03
 23 2C 41 03 23 2A 51 03 23 28 61 03 23 26 71 03
@@ -139,14 +139,14 @@ EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04
 03 2D 01 02 83 2D C1 01 13 01 01 05 6F D0 1F A8
 03 27 45 08 93 77 37 00 63 98 07 08 EF 07 80 00
 73 10 30 00 03 27 07 00 83 A7 07 00 63 0A F7 06
-13 05 10 04 97 05 00 00 93 85 85 52 97 F6 FF FF
+13 05 10 04 97 05 00 00 93 85 45 59 97 F6 FF FF
 93 86 46 99 17 F6 FF FF 13 06 C6 9C 03 A7 06 00
 83 A7 46 00 13 08 05 00 93 85 15 00 33 67 F7 00
 B7 08 01 01 63 02 07 02 13 07 00 00 23 20 E6 00
 93 07 00 00 23 22 F6 00 03 A7 06 00 83 A7 46 00
 33 67 F7 00 E3 12 07 FE 03 C5 05 00 23 A0 06 01
 23 A2 16 01 E3 1C 05 FA 13 05 30 00 EF F0 DF BE
-13 05 10 00 EF F0 5F BE 17 05 00 00 13 05 85 54
+13 05 10 00 EF F0 5F BE 17 05 00 00 13 05 45 5B
 EF F0 1F B7 13 05 30 00 EF F0 1F BD 03 29 85 02
 37 1C 00 00 97 14 00 00 93 84 C4 90 97 2B 00 00
 93 8B 4B 90 37 0B 04 00 B7 0A C0 FF 97 4D 00 00
@@ -160,10 +160,10 @@ EF F0 1F B7 13 05 30 00 EF F0 1F BD 03 29 85 02
 93 FC 0C 08 83 25 C1 00 63 80 0C 04 37 16 00 00
 13 05 0C 00 EF F0 DF 86 B3 87 84 00 73 10 0D 10
 03 A7 0D 00 23 A0 07 00 E3 1E 07 F6 23 A0 FD 00
-23 20 FA 00 6F F0 9F F7 17 05 00 00 13 05 C5 48
-EF F0 1F A9 6F F0 5F F0 17 05 00 00 13 05 45 42
+23 20 FA 00 6F F0 9F F7 17 05 00 00 13 05 85 4F
+EF F0 1F A9 6F F0 5F F0 17 05 00 00 13 05 05 49
 EF F0 1F A8 13 05 30 00 EF F0 1F AE 17 05 00 00
-13 05 C5 3D EF F0 DF A6 13 05 30 00 EF F0 DF AC
+13 05 85 44 EF F0 DF A6 13 05 30 00 EF F0 DF AC
 13 05 09 00 EF F0 5F AC F3 27 40 F1 63 96 07 16
 17 36 00 00 13 06 06 80 93 57 C6 00 13 01 01 F6
 93 97 A7 00 23 2E 11 08 23 2C 81 08 97 15 00 00
@@ -193,22 +193,29 @@ EF F0 CF F1 B7 07 00 80 33 04 F4 00 13 05 01 00
 93 D6 17 00 B3 E6 D5 00 B3 C7 D7 00 93 97 E7 01
 B3 75 F5 00 13 57 17 00 93 87 06 00 33 E7 E5 00
 B3 F6 C7 00 93 F5 17 00 B3 86 06 01 E3 96 05 FC
-03 A0 06 00 6F F0 9F FC 17 05 00 00 13 05 85 2A
+03 A0 06 00 6F F0 9F FC 17 05 00 00 13 05 45 31
 EF F0 1F 88 13 05 30 00 EF F0 1F 8E 67 80 00 00
-6F 00 C0 06 93 8F 1F 00 73 00 10 00 93 0E 90 00
-63 96 D8 03 37 0F 00 00 13 0F 0F 08 F3 2E 00 30
+6F 00 00 0B 93 8F 1F 00 73 00 10 00 93 0E 70 00
+63 8C 1E 05 93 0E 80 00 63 8C 1E 03 93 0E 90 00
+63 90 D8 07 37 0F 00 00 13 0F 0F 08 F3 2E 00 30
 B3 EE EE 01 73 90 0E 30 37 1F 00 00 13 0F 0F 80
-F3 2E 40 30 B3 EE EE 01 73 90 4E 30 F3 2E 10 34
-93 8E 4E 00 73 90 1E 34 73 00 20 30 73 00 10 00
-13 0A 1A 00 F3 2E 10 34 93 8E 4E 00 73 90 1E 34
-73 00 20 30 13 0A 1A 00 73 00 20 30 93 08 90 00
-73 00 00 00 93 02 00 00 13 03 00 00 93 03 40 06
-93 82 12 00 23 20 50 00 03 23 00 00 E3 9A 72 FE
-63 9E 62 00 13 0A 00 00 13 03 10 00 73 00 50 10
-63 16 6A 00 6F 00 80 01 63 1A 30 00 13 95 11 00
-63 00 05 00 13 65 15 00 73 00 00 00 13 05 10 00
-73 00 00 00 73 00 10 00 73 10 00 C0
-@80002AAC
+F3 2E 40 30 B3 EE EE 01 73 90 4E 30 6F 00 40 03
+37 0F 00 00 13 0F FF F7 F3 2E 00 30 B3 FE EE 01
+73 90 0E 30 6F 00 C0 01 37 FF FF FF 13 0F FF 7F
+F3 2E 40 30 B3 FE EE 01 73 90 4E 30 6F 00 40 00
+F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30
+73 00 10 00 13 0A 1A 00 F3 2E 10 34 93 8E 4E 00
+73 90 1E 34 73 00 20 30 13 0A 1A 00 73 00 20 30
+93 08 90 00 73 00 00 00 93 02 00 00 13 03 00 00
+93 03 40 06 93 82 12 00 23 20 50 00 03 23 00 00
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+73 00 50 10 63 1A 6A 02 93 08 80 00 73 00 00 00
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+6F 00 80 01 63 1A 30 00 13 95 11 00 63 00 05 00
+13 65 15 00 73 00 00 00 13 05 10 00 73 00 00 00
+73 00 10 00 73 10 00 C0
+@80002B18
 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64
 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C
 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20

diff --git a/test/priv_sec_testsuite/tests/rv32ui-v-test2.v b/test/priv_sec_testsuite/tests/rv32ui-v-test2.v
@@ -230,7 +230,7 @@ EF F0 1F 88 13 05 30 00 EF F0 1F 8E 73 10 00 3A
 73 10 10 3A B7 7E 77 77 93 8E 7E 77 73 90 2E 3A
 73 2F 20 3A 63 9A EE 4D 73 10 20 3A B7 7E 77 77
 93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 9E EE 4B
-73 10 30 3A 6F 00 40 2E 37 0F 00 00 13 0F 8F 08
+73 10 30 3A 6F 00 40 2E 37 0F 00 00 13 0F 0F 08
 F3 2E 00 30 B3 EE EE 01 73 90 0E 30 37 1F 00 00
 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01 73 90 4E 30
 6F 00 80 2B 13 04 14 00 73 00 20 30 13 06 F6 FF

diff --git a/test/priv_sec_testsuite/tests/rv64ui-p-test1.v b/test/priv_sec_testsuite/tests/rv64ui-p-test1.v
@@ -1,9 +1,9 @@
 @00010000
 6F 00 80 08 73 2F 20 34 93 0E 80 00 63 0C DF 1B
-93 0E 90 00 63 04 DF 1B 93 0E B0 00 63 04 DF 1F
-93 0E 20 00 63 02 DF 1F B7 0E 00 80 93 8E BE 00
-63 06 DF 1F B7 0E 00 80 93 8E 3E 00 63 00 DF 1F
-B7 0E 00 80 93 8E 7E 00 63 0A DF 1D 93 0E 50 00
+93 0E 90 00 63 04 DF 1B 93 0E B0 00 63 06 DF 23
+93 0E 20 00 63 04 DF 23 B7 0E 00 80 93 8E BE 00
+63 08 DF 23 B7 0E 00 80 93 8E 3E 00 63 02 DF 23
+B7 0E 00 80 93 8E 7E 00 63 0C DF 21 93 0E 50 00
 63 06 DF 17 93 0E 70 00 63 02 DF 17 93 0E 10 00
 63 0E DF 15 13 0F 00 00 63 04 0F 00 67 00 0F 00
 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53
@@ -26,22 +26,30 @@ B7 0E 00 80 93 8E 7E 00 63 0A DF 1D 93 0E 50 00
 13 05 00 00 73 00 10 00 93 02 00 00 63 8A 02 00
 73 90 52 10 B7 B2 00 00 9B 82 92 10 73 90 22 30
 73 50 00 30 97 02 00 00 93 82 42 01 73 90 12 34
-73 25 40 F1 73 00 20 30 6F 00 C0 06 93 8F 1F 00
-73 00 10 00 93 0E 90 00 63 96 D8 03 37 0F 00 00
+73 25 40 F1 73 00 20 30 6F 00 00 0B 93 8F 1F 00
+73 00 10 00 93 0E 70 00 63 8C 1E 05 93 0E 80 00
+63 8C 1E 03 93 0E 90 00 63 90 D8 07 37 0F 00 00
 13 0F 0F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30
 37 1F 00 00 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01
-73 90 4E 30 F3 2E 10 34 93 8E 4E 00 73 90 1E 34
-73 00 20 30 73 00 10 00 13 0A 1A 00 F3 2E 10 34
-93 8E 4E 00 73 90 1E 34 73 00 20 30 13 0A 1A 00
-73 00 20 30 93 08 90 00 73 00 00 00 93 02 00 00
-13 03 00 00 93 03 40 06 93 82 12 00 23 20 50 00
-03 23 00 00 E3 9A 72 FE 63 9E 62 00 13 0A 00 00
-13 03 10 00 73 00 50 10 63 16 6A 00 6F 00 C0 02
-63 14 30 02 0F 00 F0 0F 63 80 01 00 93 91 11 00
-93 E1 11 00 93 08 D0 05 13 85 01 00 93 8F 1F 00
-73 00 10 00 73 00 10 00 0F 00 F0 0F 93 01 10 00
-93 08 D0 05 13 05 00 00 73 00 10 00 73 00 10 00
-73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00
+73 90 4E 30 6F 00 40 03 37 0F 00 00 13 0F FF F7
+F3 2E 00 30 B3 FE EE 01 73 90 0E 30 6F 00 C0 01
+37 FF FF FF 13 0F FF 7F F3 2E 40 30 B3 FE EE 01
+73 90 4E 30 6F 00 40 00 F3 2E 10 34 93 8E 4E 00
+73 90 1E 34 73 00 20 30 73 00 10 00 13 0A 1A 00
+F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30
+13 0A 1A 00 73 00 20 30 93 08 90 00 73 00 00 00
+93 02 00 00 13 03 00 00 93 03 40 06 93 82 12 00
+23 20 50 00 03 23 00 00 E3 9A 72 FE 63 92 62 04
+13 0A 00 00 13 03 10 00 73 00 50 10 63 1A 6A 02
+93 08 80 00 73 00 00 00 73 00 50 10 93 08 70 00
+73 00 00 00 13 00 00 00 73 00 50 10 13 00 00 00
+73 00 50 10 13 00 00 00 6F 00 C0 02 63 14 30 02
+0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00
+93 08 D0 05 13 85 01 00 93 8F 1F 00 73 00 10 00
+73 00 10 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05
+13 05 00 00 73 00 10 00 73 00 10 00 73 10 00 C0
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00
 @00011000
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/test/priv_sec_testsuite/tests/rv64ui-p-test2.v b/test/priv_sec_testsuite/tests/rv64ui-p-test2.v
@@ -111,7 +111,7 @@ B7 7E 77 77 93 8E 7E 77 73 90 2E 3A 73 2F 20 3A
 63 84 EE 01 6F E0 4F 92 73 10 20 3A B7 7E 77 77
 93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 84 EE 01
 6F E0 8F 90 73 10 30 3A 6F 00 40 34 37 0F 00 00
-13 0F 8F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30
+13 0F 0F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30
 37 1F 00 00 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01
 73 90 4E 30 6F 00 80 31 13 04 14 00 73 00 20 30
 13 06 F6 FF 13 56 36 00 93 D5 25 00 B3 E5 C5 00