Fix: NA4 address mask lead to region greater than 4 bytes

New: Enhance test2S, testing all region types
dpretet · Nov 1, 2023 · 55f625b · 55f625b
1 parent a12eeeb
commit 55f625b
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diff --git a/doc/friscv.drawio b/doc/friscv.drawio
diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md
@@ -5,7 +5,6 @@
     - [-] Support U-mode
     - [-] Support PMP/PMA
     - [ ] Atomic operations for single core
-    - [ ] fence/fence.i instructions
     - [ ] AXI Exception management with a CLIC
     - [ ] Zc extension
 

diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
@@ -1288,12 +1288,12 @@ module friscv_control
                                      (wfi_tw)             ? 1'b1       :
                                                             '0         ;
 
-        assign illegal_csr = (priv_mode==`MMODE || !sys[`IS_CSR])    ? '0   :
-                             (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? 1'b1 : // Cycle  
-                             (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? 1'b1 : // Time  
-                             (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? 1'b1 : // Instret  
-                             (csr[11:4]=='hFC)                       ? 1'b1 : // Custom perf. registers  
-                             (csr[ 9:8]!=2'b00)                      ? 1'b1 : // M-Mode only registers 
+        assign illegal_csr = (priv_mode==`MMODE || !sys[`IS_CSR])    ? 1'b0       :
+                             (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? inst_ready : // Cycle  
+                             (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? inst_ready : // Time  
+                             (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? inst_ready : // Instret  
+                             (csr[11:4]=='hFC)                       ? inst_ready : // Custom perf. registers  
+                             (csr[ 9:8]!=2'b00)                      ? inst_ready : // M-Mode only registers 
                                                                        1'b0 ;
 
     end else begin : NO_UMODE

diff --git a/rtl/friscv_pmp_region.sv b/rtl/friscv_pmp_region.sv
@@ -69,7 +69,7 @@ module friscv_pmp_region
         logic [RLEN-1:0] mask;
         logic [XLEN-1:0] size;
     begin
-        size = 3;
+        size = 2;
         mask = '1 << size;
         base = {csr_addr, 2'b0} & mask;
         get_na4 = {mask, base};

diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw
diff --git a/test/priv_sec_testsuite/tests/env/pmp.S b/test/priv_sec_testsuite/tests/env/pmp.S
@@ -0,0 +1,27 @@
+# distributed under the mit license
+# https://opensource.org/licenses/mit-license.php
+
+.equ OFF,       0
+.equ TOR_RWX,   0x0F
+.equ TOR_RW,    0x0B
+.equ TOR_RX,    0x0D
+.equ NA4_RWX,   0x17
+.equ NA4_RW,    0x13
+.equ NA4_RX,    0x15
+.equ NAPOT_RWX, 0x1F
+.equ NAPOT_RW , 0x1B
+.equ NAPOT_RX , 0x1D
+
+.equ TOR_LRWX,   0x8F
+.equ TOR_LRW,    0x8B
+.equ TOR_LRX,    0x8D
+.equ NA4_LRWX,   0x97
+.equ NA4_LRW,    0x93
+.equ NA4_LRX,    0x95
+.equ NAPOT_LRWX, 0x9F
+.equ NAPOT_LRW , 0x9B
+.equ NAPOT_LRX , 0x9D
+
+.equ TOR,       0x08
+.equ NA4,       0x10
+.equ NAPOT,     0x18