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PyDRS v2.1.0
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@gabrielbrunheira gabrielbrunheira released this 25 Jan 15:51
· 6 commits to master since this release
v2.1.0
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Learn about vigilant mode.

What's Changed

Added:

  • SWLS resonant converter PS module specification
  • Leakage overcurrent interlock for FAC-DCDC and FAC-DCDC-EMA

Changed:

  • Fixed variable type for IIB interlock and alarm registers from FAC-DCDC-EMA PS module

Removed:

  • Obsolete ListVar list from consts

New Contributors

Full Changelog: v2.0.1...v2.1.0

Contributors

pnallin
Assets 2
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