Merge pull request #43 from cnpem-sei/PR-include-resonant-swls

Included resonant converter, fixed IIB interlocks and alarm for FAC-DCDC-EMA, included leakage overcurrent interlock for FAC-DCDC and FAC-DCDC-EMA

CHANGES.md

@@ -1,5 +1,17 @@
 # Changelog
 
+## [2.1.0] - 2022-01-18
+### Added:
+- SWLS resonant converter PS module specification
+- Leakage overcurrent interlock for FAC-DCDC and FAC-DCDC-EMA
+
+
+### Changed:
+- Fixed variable type for IIB interlock and alarm registers from FAC-DCDC-EMA PS module
+
+### Removed:
+- Obsolete ListVar list from consts
+
 ## [1.2.5] - 2022-08-15
 ### Added:
 - `read_csv_dsp_modules_bank`

src/pydrs/__init__.py

@@ -1,4 +1,4 @@
 from .pydrs import EthDRS, GenericDRS, SerialDRS  # noqa: F401
 
-__version__ = "2.0.1"
-__date__ = "21/11/2022"
+__version__ = "2.1.0"
+__date__ = "18/01/2023"

src/pydrs/base.py

@@ -26,6 +26,7 @@
     fac,
     fap,
     fbp,
+    resonant,
     num_blocks_curves_fax,
     num_blocks_curves_fbp,
     num_coeffs_dsp_modules,
@@ -1688,8 +1689,12 @@ def read_vars_common(self, vals: bytes = None) -> dict:
                 vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "V"
                 vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "V"
         else:
-            vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "%"
-            vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "%"
+            if (vars_dict["status"]["model"] == "RESONANT_SWLS"):
+                vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "Hz"
+                vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "Hz"
+            else:
+                vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "%"
+                vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "%"
 
         vars_dict["siggen_type"] = common.sig_gen_types[int(vars_dict["siggen_type"])]
         vars_dict["wfmref_sync_mode"] = common.wfmref_sync_modes[
@@ -2193,6 +2198,22 @@ def read_vars_fac_2p_dcdc_imas(self, com_add=1) -> dict:
             fac.list_2p_dcdc_imas_hard_interlocks,
         )
 
+    def read_vars_swls_resonant_converter(self) -> dict:
+        """
+        Reads SWLS resonant converter power supply variables
+
+
+        Returns
+        -------
+        dict
+            Dictionary with power supply variables
+        """
+        return self._read_vars_generic(
+            resonant.bsmp,
+            resonant.list_soft_interlocks,
+            resonant.list_hard_interlocks,
+        )
+
     def check_param_bank(self, param_file: str):
 
         ps_param_list = []

src/pydrs/consts/__init__.py

@@ -22,7 +22,7 @@
 COM_REQUEST_CURVE = "\x40"
 COM_SEND_WFM_REF = "\x41"
 
-UDC_FIRMWARE_VERSION = "0.44 2022-06-30"
+UDC_FIRMWARE_VERSION = "0.44.01    08/22"
 
 ufm_offset = {
     "serial": 0,
@@ -53,55 +53,6 @@
 num_blocks_curves_fax = [16, 16, 16]
 size_curve_block = [1024, 1024, 1024]
 
-ListVar = [
-    "iLoad1",
-    "iLoad2",
-    "iMod1",
-    "iMod2",
-    "iMod3",
-    "iMod4",
-    "vLoad",
-    "vDCMod1",
-    "vDCMod2",
-    "vDCMod3",
-    "vDCMod4",
-    "vOutMod1",
-    "vOutMod2",
-    "vOutMod3",
-    "vOutMod4",
-    "temp1",
-    "temp2",
-    "temp3",
-    "temp4",
-    "ps_OnOff",
-    "ps_OpMode",
-    "ps_Remote",
-    "ps_OpenLoop",
-    "ps_SoftInterlocks",
-    "ps_HardInterlocks",
-    "iRef",
-    "wfmRef_Gain",
-    "wfmRef_Offset",
-    "sigGen_Enable",
-    "sigGen_Type",
-    "sigGen_Ncycles",
-    "sigGenPhaseStart",
-    "sigGen_PhaseEnd",
-    "sigGen_Freq",
-    "sigGen_Amplitude",
-    "sigGen_Offset",
-    "sigGen_Aux",
-    "dp_ID",
-    "dp_Class",
-    "dp_Coeffs",
-    "ps_Model",
-    "wfmRef_PtrBufferStart",
-    "wfmRef_PtrBufferEnd",
-    "wfmRef_PtrBufferK",
-    "wfmRef_SyncMode",
-]
-
-
 hradc_variant = [
     "HRADC-FBP",
     "HRADC-FAX-A",

src/pydrs/consts/common.py

@@ -15,7 +15,7 @@
     "FAP_IMAS",
     "FAC_2P_ACDC_IMAS",
     "FAC_2P_DCDC_IMAS",
-    "Invalid",
+    "RESONANT_SWLS",
     "Invalid",
     "Invalid",
     "Invalid",

src/pydrs/consts/fac.py

@@ -85,6 +85,7 @@
     "IIB Interlock",
     "External Interlock",
     "Rack Interlock",
+    "Leakage_Overcurrent",
 ]
 
 list_dcdc_iib_interlocks = [
@@ -239,6 +240,7 @@
     "Load Waterflow",
     "Load Overtemperature",
     "IIB Itlk",
+    "Leakage_Overcurrent",
 ]
 
 list_dcdc_ema_iib_interlocks = [
@@ -376,8 +378,8 @@
     "i_leakage_iib": {"addr": 46, "format": "f", "size": 4, "egu": "A"},
     "temp_board_iib": {"addr": 47, "format": "f", "size": 4, "egu": "°C"},
     "rh_iib": {"addr": 48, "format": "f", "size": 4, "egu": "%"},
-    "iib_interlocks": {"addr": 49, "format": "f", "size": 4, "egu": ""},
-    "iib_alarms": {"addr": 50, "format": "f", "size": 4, "egu": ""},
+    "iib_interlocks": {"addr": 49, "format": "I", "size": 4, "egu": ""},
+    "iib_alarms": {"addr": 50, "format": "I", "size": 4, "egu": ""},
     "ps_alarms": {"addr": 51, "format": "I", "size": 4, "egu": ""},
 }
 

src/pydrs/consts/resonant.py

@@ -0,0 +1,17 @@
+# SWLS Resonant Converter
+list_soft_interlocks = []
+
+list_hard_interlocks = [
+    "Load Overcurrent",
+    "DCLink Overvoltage",
+    "DCLink Undervoltage",
+]
+
+bsmp = {
+    "ps_alarms": {"addr": 33, "format": "I", "size": 4, "egu": ""},
+    "i_load": {"addr": 34, "format": "f", "size": 4, "egu": "A"},
+    "v_dclink": {"addr": 35, "format": "f", "size": 4, "egu": "V"},
+    "i_load_error": {"addr": 36, "format": "f", "size": 4, "egu": "A"},
+    "freq_modulated": {"addr": 37, "format": "f", "size": 4, "egu": "Hz"},
+    "freq_modulated_ff": {"addr": 38, "format": "f", "size": 4, "egu": "Hz"},
+}