RocketChip v1.5

• DCache prioritizes misaligned above guest/page fault (#2926)
• Add hypervisor extension (#2841)
• MMU: final pte.permission page fault > final pte.ppn access exception (#2916)
• PTW: Non-leaf PTEs with D/A/U==1 are reserved (#2905)
• NMI spec updates: removed UNMI, added new mnie bit to mnstatus (#2904)
• PTW: timing L2TLB valid select write way (#2868)
• PTW timing: L2TLB PLRU select write way (#2856)
• TLToAXI4 should not block AXI4-b writeacks indefinitely (#2805)
• TLB: Deduplicate down to one OptimizationBarrier per TLBEntry (#2833)
• DCache does not block Acquire/ProbeAck by outstanding Release (#2832)
• Fix a DTIM X-prop issue (#2822)
• Prevent TLWidthWidget from generating X outputs (#2815)
• Fix x-prop issue in ScratchpadSlavePort (#2818)
• Don't attempt to cover non-existent U-mode counters (#2817)
• Suppress SCIE assertion when instruction not valid (#2816)
• Core/TLB: cacheable when supportsAcquireB (#2808)
• Fix a scratchpad ECC bug (#2804)
• ReadyValidCancelRRArbiter: non-power-of-2 round-robin select (#2798)
• add WithCoherentBusTopology to BaseFPGAConfig (#2787)
• TLMonitor: wrong opcode is checked in (unused) B Channel Get message (#2788)
• TraceGen should observe dmem.ordered when attempting a fence (#2779)
• Support timebase-frequency in the cpus node of the Device Tree (#2782)
• ReadyValidCancelRRArbiter: round-robin select wrong (#2771)
• D-Cache TileLink C-Channel drive AMBA PROT bits last connect (#2770)
• regmapper: update all regmap tests
• tilelink: buswrapper leave fromPort
• Support Chisel 3.5
• remove wake (#2847)