RocketChip v1.6

Version 1.6.0

Added

• Support for Chisel 3.5.3 (#2931, #2937, #2947, #3005)
• Support for Scala 2.12.15 (#2947)
• Properly-sized don't cares for FPU typeTag fields (#2949)
• Add a virtual argument to TLBEntry.sectorHit function (#2952)
• Support building PTW with no PTECache (#2962)
• Update IncoherentBusTopology to support multiclock and custom clocking (#2940)
• Allow forcing RocketTiles into separate PRCI groups (#2842)
• Add a WithHypervisor config (#2946)
• Add ScalaDoc documentation for I$ (#3001)

Changed

• AHPParameters and APBParameters:
  • PROT_PRIVILEDGED - This was a typo. It is now PROT_PRIVILEGED. (#2925)
• GrountTestTile: use generic BuildHellaCache key (#2919)
• copy EICG wrapper from vsrc when using Clock Gate Model (#2969)
• PTW page fault instead of access exception if PTE reserved bit set (#2913, #2934)
  • PTE_RSVD was introduced into Spike in riscv-software-src/riscv-isa-sim#750
  • Reserved PTE bits report page fault instead of access exception.
  • Add an additional bit pf to PTWResp and TLBEntryData to pipe this through.
• Have HFENCE.GVME sfence.bits.hg=1, hv=0 only target TLB entries with V=1 (and not V=0) (#2954)
• Update Instructions from riscv-opcodes and separate out rocket-specific custom instructions (#2956, #2972)
  • post riscv-opcode instruction category scheme at this PR riscv/riscv-opcodes#106
• Decode: switch to using Chisel Decode API (#2836, #2994)
• Convert toaxe.py to python3 (#3034)
• make AsyncClockGroupsKey a node generator (#2935)
• change debug module name to tlDM (#3029)
• As part of a larger migration begin refactoring files to chisel3:
  • ALU.scala (#3039)
  • AMOALU.scala (#3040)
  • Breakpoint.scala (#3041)
  • PMP.scala (#3042)
  • FormalUtils.scala (#3044)
  • Decode.scala (#3049)
  • Consts.scala (#3052)

Fixed

• Proper translation to HRProt3 in AHB Protocol (#2928)
• Assert HasFSDirty false (#2997)
• VSStatus is now read-only and dirty when RoCC is enabled (#2984)
• RocketCore: avoid false RAW/WAW hazards for integer instructions using an x register whose numeric specifier coincides with a previous instruction's f register. (#2945)
• Correct rocc_illegal to use reg_vsstatus.xs field (#2983)
• Zero out aux_pte.reserved_for_future whenever ``aux_pte.ppn` is driven (#3003)
• Prevent ILTB miss fault PTW thrashing D$ (#3004)
• Prevent nonsensical use of RVE with Hypervisor (#2988)
• Explicity outline Rocket's lack of support for haveFSDirty (#2997)
• Fix bit-width out of range issue when both Sv57 and Hypervisor are enabled (#3006)
• Fix synthesizability of RoccBlackBox with Vivado (#3035)

Removed

• Remove Object Model from Diplomacy (#2967)
• Removed RegEnable explicit arguments in preparation for changes in Chisel 3.6 (#2986)
• Removed all mentions of Travis CI and .travis.yml file (#2647)
• Remove TraceGen from `HeterogeneousTileExampleConfig (#2923)

RocketChip v1.5

• DCache prioritizes misaligned above guest/page fault (#2926)
• Add hypervisor extension (#2841)
• MMU: final pte.permission page fault > final pte.ppn access exception (#2916)
• PTW: Non-leaf PTEs with D/A/U==1 are reserved (#2905)
• NMI spec updates: removed UNMI, added new mnie bit to mnstatus (#2904)
• PTW: timing L2TLB valid select write way (#2868)
• PTW timing: L2TLB PLRU select write way (#2856)
• TLToAXI4 should not block AXI4-b writeacks indefinitely (#2805)
• TLB: Deduplicate down to one OptimizationBarrier per TLBEntry (#2833)
• DCache does not block Acquire/ProbeAck by outstanding Release (#2832)
• Fix a DTIM X-prop issue (#2822)
• Prevent TLWidthWidget from generating X outputs (#2815)
• Fix x-prop issue in ScratchpadSlavePort (#2818)
• Don't attempt to cover non-existent U-mode counters (#2817)
• Suppress SCIE assertion when instruction not valid (#2816)
• Core/TLB: cacheable when supportsAcquireB (#2808)
• Fix a scratchpad ECC bug (#2804)
• ReadyValidCancelRRArbiter: non-power-of-2 round-robin select (#2798)
• add WithCoherentBusTopology to BaseFPGAConfig (#2787)
• TLMonitor: wrong opcode is checked in (unused) B Channel Get message (#2788)
• TraceGen should observe dmem.ordered when attempting a fence (#2779)
• Support timebase-frequency in the cpus node of the Device Tree (#2782)
• ReadyValidCancelRRArbiter: round-robin select wrong (#2771)
• D-Cache TileLink C-Channel drive AMBA PROT bits last connect (#2770)
• regmapper: update all regmap tests
• tilelink: buswrapper leave fromPort
• Support Chisel 3.5
• remove wake (#2847)

RocketChip v1.4

Rocket

• [CSR] add vcsr and move vxrm/vxstat from fcsr to that register set (#2400, #2422)
• [CSR] disallow writes to MSTATUS.XS (#2508)
• [CSR] expand TracedInstruction.cause to xLen (#2548)
• [CSR][mstatus] implement updated MPRV from priv-1.12 (#2206)
• [CSR] add `mcountinhibit from priv-1.11 (#2693)
  • ignore PAUSE when mcountinhibit(0) === 1 (#2700)
• [CSR] Comply with priv spec by resetting and initializing mcause to 0 (#2333)
• [events] add SuperscalarEventSets (#2337, #2506)
• [events] make fields public for tapping signals (#2464, #2524)
• [i$] fix ccover bug to cover all beats of D channel corruption #2755
• [d$] updates
  • fix elaboration with < 4 MiB of physical address space (#2367)
  • guarantee no-alloc accesses are ordered even if aliased (#2358)
  • [ecc] fixed a rare bug where under the right conditions stores to the same word resulted in one store detecting an error while the other does not (#2458)
  • [HellaCache] introduce subWordBits param to support subbanking (#2645)
  • support specifying cache index when aliasing is possible (#2697, #2730)
  • reduce latency on inclusion and coherence misses by allowing D$ to voluntarily release (aka "noisy drop") cache lines (#2696)
    • follow-up to fix deadlock (#2714)
    • follow-up to fix performance (#2739)
• distinguish a supervisor mode that does not use MMU/VM (#2422, #2499)
• [hartid]
  • fixed an issue where the Rocket core's placement would be impacted by non-constant hartid (#2432)
  • add a diplomatic node for assigning hartid (#2447)
• [Replacement][PseudoLRU] fix performance issue with PseudoLRU for replacements when number of ways is not a power of 2 (#2493, #2498)
• [Replacement][d$] configure replacement policy with parameter to indicate wheteher policy is used on a per-set basis or a global basis (#2656)
• [PTW]
  • replace round robin arbitration with static arbitration (#2433)
  • fixed a bug where an L2TLB write would almost always block the next L2TLB search when MMU and clock gating were enabled (#2601)
  • wait for L2TLB to refill before searching (#2619)
  • [PTWPerfEvents] add (unused) Performance Monitor Events for L2TLB hit and PTE Cache Miss/Hit (#2668, #2688, #2692)
  • enable configurable set-associtive L2 TLB (#2748, #2753)
    • default configuration is direct-mapped
• enable Sv48 setting page levels equal to 4 (#2434)
• [PMP] remove NA4 coverpoint for pmp granularity > 4 (#2625)
• [TLB]
  • check PutPartial support separately from PutFull (#2503)
  • fix a rare refill/invalidate race condition (#2534)
  • configure L1 D/I TLBs by set, entry, and replacement policy (#2574, #2621)
  • add params nTLBBasePageSectors and nTLBSuperpages for both I and D TLBs #2595
• [CoreMonitor]
  • add privilege mode and exception signals (#2387)
  • now prints only retired instructions (#2372)
  • separate wren into wrenx/wrenf for integer/float (#2423)
  • Add [CoreMonitorBundle] for [FPU] floating point registers (#2538, #2541, #2546, #2589)
• [FPU] Zfh extension, option for Half-Precision unit (#2723)
  • replaces singleIn and singleOut with typeTagIn and typeTagOut
• preliminary RV32Zfh extension support (#2359)
• [RVV] -> 0.9 -> 1.0 (#2477, #2484, #2396, #2552, #2576)
  • Fractional LMUL
  • Tail-agnostic/mask-agnostic bits
  • EEW loads/stores
  • Some encoding changes
  • tighten fractional LMUL-SEW constraint
  • Instructions: add new and update RISC-V vector extension opcodes
  • reorder fields in vtype
• add B extension opcodes and object model description (#2678)
• fixed an issue where multiplierIO was unclonable (#2331)

Devices

• [PLIC] add support for PLIC elaboration even when nDevices == 0 (#2351)
• [PLIC] fix off-by-one for priority register description (#2718)
• [BuildInDevices] introduce case class parameters to Zero and Error device #2684
  • make instantiation of buffers optional
  • allow for optional instantiation of CacheCork
• [BasicBusBlocker] convert to chisel3, add scala-doc, add factory companion object (#2630)
• [PhysicalFilter] added scaladoc and RegFieldDesc (#2685)
• [BEU]
  • added a Device Tree description for the bus error unit (#2373)
  • report Corrupt+Denied on I-Fetch (#2482)

PRCI

• [ResetSynchronizer][ClockGroupResetSynchronizer] add a pair of diplomatic reset synchronizers (#2666)
  • replaced IdentityNodes with AdapterNodes (#2689)
• wrap Tiles in PRCI Domains (#2550)
  • contains logic related to power, reset, clock, and interrupt
• define ResetCrossingType and use with BlockDuringReset in TilePRCIDomain (#2641)
  • analogous to ClockCrossingType. Currently, there are two crossing types: NoResetCrossing and StretchedResetCrossing(cycles: Int)
  • introduces Blockable util
• Synchronizer primitive changes (#2212)
  • introduction of ClockCrossingReg
  • _SynchronizerShiftReg requires synchronizer depth > 1
  • deprecate IntXing and IntSyncCrossingSink
  • deprecate SyncResetSynchronizerShiftReg
• [SynchronizerPrimitiveShiftReg] correct the dedup behavior for the *ResetSynchronizerPrimitiveShiftReg so you only end up with one copy (#2547)
• add partial multiple reset scheme support (#2375)
• AsyncResetReg: use chisel3 async resets (#2397)
• Async Reset support for Atomics, FPU, and TLBroadcast (#2362)
• [ResetStretcher][PRCI] add reset stretcher for Async Reset systems (#2566)
• ClockGroupDriverParameters: allow for a configurable drive function for driving asynchronous clock groups with IO other than the implicit clock (#2319)
• [ClockDivider] fixed bug where clock divider's source and sink functions always divided by two (#2610)
• [InterruptBusWrapper] update synchronizer API #2640
  • replaces using IntXing in a synchronize method with to and from methods
  • this is to ensure synchronized registers are always put in the destination clock domain

Tile

• [notification] provide reset values for cease and wfi (#2449)
• [notification][CSR] Block wfi, halt, cease, and other valid signals during asynchronous reset (#2611)
  • trace.valid of CSR changed to async-reset delay (#2613)
• [notification][WFI] expose WFI from core (#2315)
• [i$] fixed bug where cease signal was asserted before potential glitching in I$ clock finished. Add an assertion to cease signal. (#2419, h...