Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

xcup: Enable global clock routing #53

Open
wants to merge 5 commits into
base: main
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -12,4 +12,4 @@
url = https://github.com/SymbiFlow/XilinxUnisimLibrary.git
[submodule "third_party/python-fpga-interchange"]
path = third_party/python-fpga-interchange
url = https://github.com/SymbiFlow/python-fpga-interchange
url = https://github.com/gatecat/python-fpga-interchange
2 changes: 1 addition & 1 deletion environment.yml
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ dependencies:
- litex-hub::prjxray-tools=0.1_2842_g6867429c=20210301_104249
- litex-hub::prjxray-db=0.0_252_g8372b58=20210622_220029
- litex-hub::yosys=0.9_5457_gc6681508=20210615_141355_py38
- litex-hub::nextpnr-fpga_interchange=v0.0_3690_g2c459961=20210625_074838
- litex-hub::nextpnr-fpga_interchange=v0.0_3699_g1a5bb7b8=20210625_074838
- litex-hub::iverilog=s20150603_0957_gad862020=20201120_145821
- litex-hub::prjoxide=v0.0_376_gd0b0340=20210624_125028
- swig
Expand Down
5 changes: 4 additions & 1 deletion tests/common/dcp_vivado.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,10 @@ set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
# Reports
report_utilization -file $::env(OUTPUT_DIR)/utilization.rpt
report_clock_utilization -file $::env(OUTPUT_DIR)/clock_utilization.rpt
report_timing_summary -datasheet -max_paths 10 -file $::env(OUTPUT_DIR)/timing_summary.rpt
if { $::env(ARCH) != "xcup" } {
# This segfaults Vivado on the counter-zcu104 example...
report_timing_summary -datasheet -max_paths 10 -file $::env(OUTPUT_DIR)/timing_summary.rpt
}
report_power -file $::env(OUTPUT_DIR)/power.rpt
report_route_status -file $::env(OUTPUT_DIR)/route_status.rpt

Expand Down
6 changes: 6 additions & 0 deletions tests/common/remap_xcup.v
Original file line number Diff line number Diff line change
Expand Up @@ -17,3 +17,9 @@ module BUF(input I, output O);
LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));

endmodule

module BUFG(input I, output O);

BUFGCE #(.SIM_DEVICE("ULTRASCALE_PLUS")) _TECHMAP_REPLACE_ (.I(I), .CE(1'b1), .O(O));

endmodule
2 changes: 1 addition & 1 deletion tests/common/synth_xcup.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ foreach src $::env(SOURCES) {
read_verilog $src
}

synth_xilinx -flatten -noclkbuf -nolutram -nowidelut -nosrl -nocarry -nodsp -arch xcup
synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp -arch xcup

if { $::env(TECHMAP) != "" } {
techmap -map $::env(TECHMAP)
Expand Down