chipsalliance · kgugala · Jan 28, 2025 · Jan 23, 2025 · Jan 23, 2025 · Jan 24, 2025
diff --git a/.github/scripts/run_regression_test.sh b/.github/scripts/run_regression_test.sh
@@ -3,6 +3,19 @@
 SELF_DIR="$(dirname $(readlink -f ${BASH_SOURCE[0]}))"
 . ${SELF_DIR}/common.inc.sh
 
+trap report_status EXIT
+
+report_status(){
+    rc=$?
+    if [ $rc != 0 ]; then
+        echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_RED}FAILED${COLOR_CLEAR}"
+    else
+        mv ${DIR}/coverage.dat ${RESULTS_DIR}/
+        echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}"
+    fi
+    exit $rc
+}
+
 run_regression_test(){
     # Run a regression test with coverage collection enabled
     # Args:
@@ -60,14 +73,6 @@ run_regression_test(){
     # Run the test
     mkdir -p ${DIR}
     make -j`nproc` -C ${DIR} -f $RV_ROOT/tools/Makefile verilator $EXTRA_ARGS CONF_PARAMS="${PARAMS}" TEST=${NAME} COVERAGE=${COVERAGE} 2>&1 | tee ${LOG}
-    if [ ! -f "${DIR}/coverage.dat" ]; then
-        echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_RED}FAILED${COLOR_CLEAR}"
-        exit 1
-    else
-        mv ${DIR}/coverage.dat ${RESULTS_DIR}/
-        echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}"
-        exit 0
-    fi
 }
 
 # Example usage

diff --git a/testbench/asm/dside_access_region_prediction_error.s b/testbench/asm/dside_access_region_prediction_error.s
@@ -3,19 +3,17 @@
 dside_load_region_prediction_error:
     li x4, 0x5
     li x5, 0x5
-    // this assumes that RV_PIC_BASE_ADDR is as high in the region
-    // as realistically allowed, e.g. 0xffff8000, this allows us
-    // to construct an address that will overflow to another region
-    // when offset is used in an 'lw' instruction: 0xfffffffc + 0x4
-    li x2, RV_PIC_BASE_ADDR + 0x7ffc
+    // We take a large address that will overflow to another region
+    // when offset is used in an 'lw' instruction: 0xFFFFFFFC + 0x4
+    li x2, 0xFFFFFFFC
     lw x2, 0x4(x2)
     j fail_if_not_serviced
 
 dside_store_region_prediction_error:
     li x4, 0x7
     li x5, 0x5
     // same as in load region prediction error
-    li x2, RV_PIC_BASE_ADDR + 0x7ffc
+    li x2, 0xFFFFFFFC
     sw x2, 0x4(x2)
     j fail_if_not_serviced
 

diff --git a/testbench/asm/tb.h b/testbench/asm/tb.h
@@ -2,8 +2,8 @@
 
 #define TRIGGER_NMI 0x80
 #define LOAD_NMI_ADDR 0x81
-#define TRIGGER_DBUS_FAULT 0x82
-#define TRIGGER_IBUS_FAULT 0x83
 #define TRIGGER_SOFT_INT 0x84
 #define TRIGGER_TIMER_INT 0x85
-#define TRIGGER_EXT_INT1 0x86
+#define TRIGGER_EXT_INT1 0x86
+#define TRIGGER_DBUS_FAULT 0x87
+#define TRIGGER_IBUS_FAULT 0x88
diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv
@@ -114,7 +114,7 @@ module tb_top
     logic                       rst_l;
 `endif
     logic                       porst_l;
-    logic [pt.PIC_TOTAL_INT:1]  ext_int;
+    logic [pt.PIC_TOTAL_INT:1]  extintsrc_req;
     logic                       nmi_int;
     logic                       timer_int;
     logic                       soft_int;
@@ -123,8 +123,6 @@ module tb_top
     logic        [31:0]         nmi_vector;
     logic        [31:1]         jtag_id;
 
-    logic [pt.PIC_TOTAL_INT:1]  extintsrc_req;
-
     logic        [31:0]         ic_haddr        ;
     logic        [2:0]          ic_hburst       ;
     logic                       ic_hmastlock    ;
@@ -775,6 +773,10 @@ module tb_top
     logic [1:0] ifu_axi_rresp_override;
 
     always @(negedge core_clk) begin
+        nmi_assert_int <= nmi_assert_int >> 1;
+        soft_int <= 0;
+        timer_int <= 0;
+        extintsrc_req[1] <= 0;
         cycleCnt <= cycleCnt+1;
         // Test timeout monitor
         if(cycleCnt == MAX_CYCLES) begin
@@ -791,16 +793,19 @@ module tb_top
         // data[7:0] == 0x81 - set ext irq line index given by data[15:8]
         // data[7:0] == 0x82 - clean NMI, timer and soft irq lines to bits data[8:10]
         // data[7:0] == 0x83 - set NMI, timer and soft irq lines to bits data[8:10]
+        // data[7:0] == 0x86 - Trigger external interrupt
+        // data[7:0] == 0x87 - (AXI4) Trigger data bus error on the next load/store
+        // data[7:0] == 0x88 - (AXI4) Trigger instruction bus error on the next load/store
         // data[7:0] == 0x90 - clear all interrupt request signals
         if(mailbox_write && (mailbox_data[7:0] >= 8'h80 && mailbox_data[7:0] < 8'h87)) begin
             if (mailbox_data[7:0] == 8'h80) begin
                 if (mailbox_data[15:8] > 0 && mailbox_data[15:8] < pt.PIC_TOTAL_INT && nmi_assert_int == 4'b0000)
-                    ext_int[mailbox_data[15:8]] <= 1'b0;
+                    extintsrc_req[mailbox_data[15:8]] <= 1'b0;
                 nmi_assert_int <= 4'b1111;
             end
             if (mailbox_data[7:0] == 8'h81) begin
                 if (mailbox_data[15:8] > 0 && mailbox_data[15:8] < pt.PIC_TOTAL_INT)
-                    ext_int[mailbox_data[15:8]] <= 1'b1;
+                    extintsrc_req[mailbox_data[15:8]] <= 1'b1;
                 nmi_vector[31:1] <= {mailbox_data[31:8], 7'h00};
             end
             if (mailbox_data[7:0] == 8'h82 && nmi_assert_int == 4'b0000) begin
@@ -824,11 +829,12 @@ module tb_top
             end
         end
         if(mailbox_write && (mailbox_data[7:0] == 8'h90)) begin
-            ext_int        <= {pt.PIC_TOTAL_INT-1{1'b0}};
+            extintsrc_req  <= {pt.PIC_TOTAL_INT-1{1'b0}};
             nmi_assert_int <= 4'b0000;
             timer_int      <= 1'b0;
             soft_int       <= 1'b0;
         end
+        // end
         // ECC error injection
         if(mailbox_write && (mailbox_data[7:0] == 8'he0)) begin
             $display("Injecting single bit ICCM error");
@@ -868,28 +874,21 @@ module tb_top
         end
         else if(mailbox_write && mailbox_data[7:0] == 8'h1) begin
             $display("TEST_FAILED");
-            $finish;
+            `ifdef TB_SILENT_FAIL
+                $finish;
+            `else
+                $fatal;
+            `endif // TB_SILENT_FAIL
         end
-
-        // Custom test commands
-        // Available commands (that can be written into address mem_mailbox_testcmd) are:
-        // 8'h80 - trigger NMI
-        // 8'h81 - set NMI handler address (mailbox_data[31:8] is the address of a handler,
-        //         i.e. it must be 256 byte-aligned)
-        // 8'h82 - trigger data bus error on the next load/store
-        nmi_assert_int <= nmi_assert_int >> 1;
-        soft_int <= 0;
-        timer_int <= 0;
-        extintsrc_req[1] <= 0;
     end
 
     `ifdef RV_BUILD_AXI4
     // this needs to be a separate block due to sensitivity to other signals
     always @(negedge core_clk or lsu_axi_bvalid or lsu_axi_rvalid or ifu_axi_rvalid or ifu_axi_rid) begin
-        if (mailbox_write && mailbox_data[7:0] == 8'h82)
+        if (mailbox_write && mailbox_data[7:0] == 8'h87)
             // wait for current transaction that to complete to not trigger error on it
             @(negedge lsu_axi_bvalid) next_dbus_error <= 1;
-        if (mailbox_write && mailbox_data[7:0] == 8'h83)
+        if (mailbox_write && mailbox_data[7:0] == 8'h88)
             @(negedge ifu_axi_rvalid or ifu_axi_rid) next_ibus_error <= 1;
         // turn off forcing dbus error after a transaction
         if (next_dbus_error)
@@ -989,9 +988,9 @@ module tb_top
         abi_reg[30] = "t5";
         abi_reg[31] = "t6";
 
-        ext_int     = {pt.PIC_TOTAL_INT-1{1'b0}};
-        timer_int   = 0;
-        soft_int    = 0;
+        extintsrc_req = {pt.PIC_TOTAL_INT-1{1'b0}};
+        timer_int     = 0;
+        soft_int      = 0;
 
     // tie offs
         jtag_id[31:28] = 4'b1;
@@ -1000,7 +999,6 @@ module tb_top
         reset_vector   = `RV_RESET_VEC;
         nmi_assert_int = 0;
         nmi_vector     = 32'hee000000;
-        extintsrc_req  = 0;
 
         $readmemh("program.hex",  lmem.mem);
         $readmemh("program.hex",  imem.mem);
@@ -1322,7 +1320,7 @@ veer_wrapper rvtop_wrapper (
     .dma_axi_rlast          (dma_axi_rlast),
 `endif
     .timer_int              ( timer_int ),
-    .extintsrc_req          ( ext_int ),
+    .extintsrc_req          ( extintsrc_req ),
 
     .lsu_bus_clk_en         (lsu_bus_clk_en),// Clock ratio b/w cpu core clk & AHB master interface
     .ifu_bus_clk_en         ( 1'b1  ),// Clock ratio b/w cpu core clk & AHB master interface

diff --git a/testbench/tests/csr_misa/csr_misa.c b/testbench/tests/csr_misa/csr_misa.c
@@ -1,4 +1,5 @@
 #include <stdio.h>
+#include <defines.h>
 
 #define read_csr(csr) ({ \
     unsigned long res; \
@@ -7,8 +8,17 @@
 })
 
 int main () {
-
-    const unsigned long golden = 0x40101104;
+    #ifdef RV_USER_MODE
+    const unsigned int user_mode = 1;
+    #else
+    const unsigned int user_mode = 0;
+    #endif
+    const unsigned int compressed_ext = 1;
+    const unsigned int rv32i_base_isa = 1;
+    const unsigned int int_mult_ext = 1;
+    const unsigned int base = 1;
+    const unsigned long golden = base << 30 | user_mode << 20  | int_mult_ext << 12 | \
+                                 rv32i_base_isa << 8 | compressed_ext << 2;
 
     // Read and print misa
     unsigned long misa = read_csr(misa);

diff --git a/tools/Makefile b/tools/Makefile
@@ -119,6 +119,11 @@ ifdef assert
  ASSERT_DEFINES = +define+RV_ASSERT_ON
 endif
 
+# Prevent testbench from returning a non-zero exit code
+ifdef tb_silent_fail
+ TB_SILENT_FAIL = +define+TB_SILENT_FAIL
+endif
+
 # provide specific link file
 ifeq (,$(wildcard $(TEST_DIR)/$(TEST).ld))
 	LINK = $(BUILD_DIR)/link.ld
@@ -193,7 +198,7 @@ ${BUILD_DIR}/defines.h:
 verilator-build: ${TBFILES} ${BUILD_DIR}/defines.h $(TB_VERILATOR_SRCS)
 	$(VERILATOR)  --cc -CFLAGS "${CFLAGS}" --coverage-max-width 20000 $(defines) \
 	  $(includes) -I${RV_ROOT}/testbench -f ${RV_ROOT}/testbench/flist \
-	  $(VERILATOR_SKIP_WARNINGS) $(VERILATOR_EXTRA_ARGS) ${TBFILES} --top-module tb_top \
+	  $(VERILATOR_SKIP_WARNINGS) $(VERILATOR_EXTRA_ARGS) ${TB_SILENT_FAIL} ${TBFILES} --top-module tb_top \
 	  -exe $(TB_VERILATOR_SRCS) --autoflush --timing $(VERILATOR_DEBUG) $(VERILATOR_COVERAGE) -fno-table
 	cp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir/
 	$(MAKE) -e -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)

diff --git a/tools/renode/build-all-tests.sh b/tools/renode/build-all-tests.sh
@@ -9,7 +9,7 @@ mkdir -p build
 cd build
 for test in ${tests}; do
     test_name=$(basename ${test})
-    make CFLAGS=-DUSE_HTIF=false -f ${RV_ROOT}/tools/Makefile TEST=${test_name} program.hex
+    make CFLAGS=-DUSE_HTIF=false -f ${RV_ROOT}/tools/Makefile TEST=${test_name} USER_MODE=1 program.hex
     mv ${test_name}.exe ../${test_name}.elf
     make -f ${RV_ROOT}/tools/Makefile clean
 done

diff --git a/tools/riscv-dv/Makefile b/tools/riscv-dv/Makefile
@@ -45,6 +45,9 @@ VERILATOR       = verilator
 VERILATOR_CFLAGS= "-std=c++14"
 VERILATOR_INC   = -I$(WORK_DIR) -I$(RV_ROOT)/testbench
 VERILATOR_EXE   = $(RV_ROOT)/testbench/test_tb_top.cpp
+# Set `TB_SILENT_FAIL` as generated instruction sequences may cause TB errors
+# Errors are to be reported when execution flows discrepancy is encountered
+VERILATOR_EXTRA_DEFS = +define+TB_SILENT_FAIL
 
 HDL_FILES = $(WORK_DIR)/common_defines.vh \
             $(WORK_DIR)/el2_pdef.vh \
@@ -116,7 +119,7 @@ $(WORK_DIR)/defines.h: | $(WORK_DIR)
 
 # Verilated testbench rules
 $(WORK_DIR)/verilator/Vtb_top.mk: $(WORK_DIR)/defines.h
-	$(VERILATOR) --cc -CFLAGS $(VERILATOR_CFLAGS) $(VERILATOR_INC) \
+	$(VERILATOR) --cc -CFLAGS $(VERILATOR_CFLAGS) $(VERILATOR_INC) $(VERILATOR_EXTRA_DEFS)\
         $(HDL_FILES) -f $(RV_ROOT)/testbench/flist --top-module tb_top \
 		-exe $(VERILATOR_EXE) -Wno-WIDTH -Wno-UNOPTFLAT $(VERILATOR_NOIMPLICIT) --autoflush \
 		--timing $(VERILATOR_COVERAGE) -fno-table -Wno-LATCH\