Update testbench fail condition #374
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Update testbench and renode.test to use generated configuration as a reference for expected MISA read value. Signed-off-by: Wiktoria Kuna <[email protected]>
Likely due to RV_PIC_BASE_ADDR value changing, the 'dside_access_region_prediction_error' test would no longer cause an overflow and hence not cause a prediction error. Signed-off-by: Wiktoria Kuna <[email protected]>
Make testbench throw 'fatal' on fail by default. Add a 'tb_silent_fail' flag to force the exit status to 0 (for RISCV-DV tests). Signed-off-by: Wiktoria Kuna <[email protected]>
Attempting to shift the nmi_assert_int at the end of negedge block would cause its overwrite. Similarily, de-asserting int logic at the end of the block would cause it to never be raised. Signed-off-by: Wiktoria Kuna <[email protected]>
Rename 'ext_int' to connect both 'ext_int' and the 'extintsrc_req' to the VeeR wrapper. Signed-off-by: Wiktoria Kuna <[email protected]>
Signed-off-by: Wiktoria Kuna <[email protected]>
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Coverage report for this PR is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/374/coverage_dashboard/all, documentation is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/374/docs_rendered/html |
This was referenced Jan 28, 2025
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Update
run_regression_test.shscript accordinglyFollows up #373.