riscv64: Fix missing extensions for 8/16-bit div/rem

This was mistakenly left out of my recent refactor for remainder/division. Closes bytecodealliance#7245
alexcrichton · Oct 17, 2023 · 8bea712 · 8bea712
1 parent 5481c1f
commit 8bea712
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Showing 2 changed files with 13 additions and 3 deletions.
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -556,7 +556,7 @@
 (rule 1 (lower (has_type (fits_in_16 ty) (sdiv x y @ (iconst imm))))
   (if-let $true (has_m))
   (if (safe_divisor_from_imm64 ty imm))
-  (rv_divw (sext x) y))
+  (rv_divw (sext x) (sext y)))
 
 (rule 2 (lower (has_type $I32 (sdiv x y)))
   (if-let $true (has_m))
@@ -604,7 +604,7 @@
 (rule 1 (lower (has_type (fits_in_16 ty) (urem x y @ (iconst imm))))
   (if-let $true (has_m))
   (if (safe_divisor_from_imm64 ty imm))
-  (rv_remuw (zext x) y))
+  (rv_remuw (zext x) (zext y)))
 
 (rule 2 (lower (has_type $I32 (urem x y)))
   (if-let $true (has_m))
@@ -633,7 +633,7 @@
 (rule 1 (lower (has_type (fits_in_16 ty) (srem x y @ (iconst imm))))
   (if-let $true (has_m))
   (if (safe_divisor_from_imm64 ty imm))
-  (rv_remw (sext x) y))
+  (rv_remw (sext x) (sext y)))
 
 (rule 2 (lower (has_type $I32 (srem x y)))
   (if-let $true (has_m))

diff --git a/cranelift/filetests/filetests/runtests/urem.clif b/cranelift/filetests/filetests/runtests/urem.clif
@@ -135,3 +135,13 @@ block0(v0: i8):
 ; run: %urem_imm_i8(-19) == 0
 ; run: %urem_imm_i8(0xC0) == 0
 ; run: %urem_imm_i8(0x80) == 2
+
+
+function %constant_inputs() -> i8  {
+block0:
+    v3 = iconst.i8 208
+    v11 = urem v3, v3  ; v3 = 208, v3 = 208
+    return v11
+}
+
+; run: %constant_inputs() == 0