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riscv: Delete AdjustSp instruction (bytecodealliance#7265)
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@afonso360
afonso360 authored Oct 17, 2023
1 parent 9e4d446 commit 5481c1f
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Showing 145 changed files with 1,938 additions and 1,924 deletions.
36 changes: 25 additions & 11 deletions cranelift/codegen/src/isa/riscv64/abi.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -318,12 +318,29 @@ impl ABIMachineSpec for Riscv64MachineDeps {

fn gen_sp_reg_adjust(amount: i32) -> SmallInstVec<Inst> {
let mut insts = SmallVec::new();

if amount == 0 {
return insts;
}
insts.push(Inst::AdjustSp {
amount: amount as i64,
});

if let Some(imm) = Imm12::maybe_from_i64(amount as i64) {
insts.push(Inst::AluRRImm12 {
alu_op: AluOPRRI::Addi,
rd: writable_stack_reg(),
rs: stack_reg(),
imm12: imm,
})
} else {
let tmp = writable_spilltmp_reg();
insts.extend(Inst::load_constant_u64(tmp, amount as i64 as u64));
insts.push(Inst::AluRRR {
alu_op: AluOPRRR::Add,
rd: writable_stack_reg(),
rs1: tmp.to_reg(),
rs2: stack_reg(),
});
}

insts
}

Expand All @@ -346,7 +363,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
// sd ra,8(sp) ;; save ra.
// sd fp,0(sp) ;; store old fp.
// mv fp,sp ;; set fp to sp.
insts.push(Inst::AdjustSp { amount: -16 });
insts.extend(Self::gen_sp_reg_adjust(-16));
insts.push(Self::gen_store_stack(
StackAMode::SPOffset(8, I64),
link_reg(),
Expand Down Expand Up @@ -394,7 +411,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
writable_fp_reg(),
I64,
));
insts.push(Inst::AdjustSp { amount: 16 });
insts.extend(Self::gen_sp_reg_adjust(16));
}

if call_conv == isa::CallConv::Tail && frame_layout.stack_args_size > 0 {
Expand Down Expand Up @@ -472,9 +489,8 @@ impl ABIMachineSpec for Riscv64MachineDeps {
));
cur_offset += 8
}
insts.push(Inst::AdjustSp {
amount: -(stack_size as i64),
});

insts.extend(Self::gen_sp_reg_adjust(-(stack_size as i32)));
}
insts
}
Expand All @@ -487,9 +503,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
let mut insts = SmallVec::new();
let stack_size = frame_layout.fixed_frame_storage_size + frame_layout.clobber_size;
if stack_size > 0 {
insts.push(Inst::AdjustSp {
amount: stack_size as i64,
});
insts.extend(Self::gen_sp_reg_adjust(stack_size as i32));
}
let mut cur_offset = 8;
for reg in &frame_layout.clobbered_callee_saves {
Expand Down
2 changes: 0 additions & 2 deletions cranelift/codegen/src/isa/riscv64/inst.isle
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Original file line number Diff line number Diff line change
Expand Up @@ -103,8 +103,6 @@
(from_bits u8)
(to_bits u8))

(AdjustSp
(amount i64))
(Call
(info BoxCallInfo))

Expand Down
26 changes: 1 addition & 25 deletions cranelift/codegen/src/isa/riscv64/inst/emit.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -238,7 +238,6 @@ impl Inst {
| Inst::Rets { .. }
| Inst::Ret { .. }
| Inst::Extend { .. }
| Inst::AdjustSp { .. }
| Inst::Call { .. }
| Inst::CallInd { .. }
| Inst::ReturnCall { .. }
Expand Down Expand Up @@ -1200,29 +1199,7 @@ impl Inst {
.into_iter()
.for_each(|i| i.emit(&[], sink, emit_info, state));
}
&Inst::AdjustSp { amount } => {
if let Some(imm) = Imm12::maybe_from_i64(amount) {
Inst::AluRRImm12 {
alu_op: AluOPRRI::Addi,
rd: writable_stack_reg(),
rs: stack_reg(),
imm12: imm,
}
.emit(&[], sink, emit_info, state);
} else {
let tmp = writable_spilltmp_reg();
let mut insts = Inst::load_constant_u64(tmp, amount as u64);
insts.push(Inst::AluRRR {
alu_op: AluOPRRR::Add,
rd: writable_stack_reg(),
rs1: tmp.to_reg(),
rs2: stack_reg(),
});
insts
.into_iter()
.for_each(|i| i.emit(&[], sink, emit_info, state));
}
}

&Inst::Call { ref info } => {
if info.opcode.is_call() {
sink.add_call_site(info.opcode);
Expand Down Expand Up @@ -3227,7 +3204,6 @@ impl Inst {
from_bits,
to_bits,
},
Inst::AdjustSp { .. } => self,

Inst::Call { .. } => self,
Inst::CallInd { mut info } => {
Expand Down
4 changes: 0 additions & 4 deletions cranelift/codegen/src/isa/riscv64/inst/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -417,7 +417,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
collector.reg_use(rn);
collector.reg_def(rd);
}
&Inst::AdjustSp { .. } => {}
&Inst::Call { ref info } => {
for u in &info.uses {
collector.reg_fixed_use(u.vreg, u.preg);
Expand Down Expand Up @@ -1515,9 +1514,6 @@ impl Inst {
format!("slli {rd},{rn},{shift_bits}; {op} {rd},{rd},{shift_bits}")
};
}
&MInst::AdjustSp { amount } => {
format!("{} sp,{:+}", "add", amount)
}
&MInst::Call { ref info } => format!("call {}", info.dest.display(None)),
&MInst::CallInd { ref info } => {
let rd = format_reg(info.rn, allocs);
Expand Down
4 changes: 2 additions & 2 deletions cranelift/filetests/filetests/isa/riscv64/amodes-fp.clif
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Original file line number Diff line number Diff line change
Expand Up @@ -11,15 +11,15 @@ block0:
}

; VCode:
; add sp,-16
; addi sp,sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; block0:
; ld a0,24(fp)
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; addi sp,sp,16
; ret
;
; Disassembled:
Expand Down
24 changes: 12 additions & 12 deletions cranelift/filetests/filetests/isa/riscv64/bitops.clif
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Original file line number Diff line number Diff line change
Expand Up @@ -184,13 +184,13 @@ block0(v0: i128):
}

; VCode:
; add sp,-16
; addi sp,sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; sd s6,-8(sp)
; sd s11,-16(sp)
; add sp,-16
; addi sp,sp,-16
; block0:
; mv s11,a1
; mv a1,a0
Expand All @@ -199,12 +199,12 @@ block0(v0: i128):
; mv a4,s11
; rev8 s6,a4##step=a2 tmp=a3
; brev8 a0,s6##tmp=a4 tmp2=a5 step=a2 ty=i64
; add sp,+16
; addi sp,sp,16
; ld s6,-8(sp)
; ld s11,-16(sp)
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; addi sp,sp,16
; ret
;
; Disassembled:
Expand Down Expand Up @@ -1853,12 +1853,12 @@ block0(v0: i128, v1: i128):
}

; VCode:
; add sp,-16
; addi sp,sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; sd s11,-8(sp)
; add sp,-16
; addi sp,sp,-16
; block0:
; andi a5,a2,63
; li a3,64
Expand All @@ -1871,11 +1871,11 @@ block0(v0: i128, v1: i128):
; srl a4,a1,a5
; andi a5,a2,127
; select [a0,a1],[a4,zero],[s11,a4]##condition=(a5 uge a3)
; add sp,+16
; addi sp,sp,16
; ld s11,-8(sp)
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; addi sp,sp,16
; ret
;
; Disassembled:
Expand Down Expand Up @@ -1971,12 +1971,12 @@ block0(v0: i128, v1: i128):
}

; VCode:
; add sp,-16
; addi sp,sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; sd s11,-8(sp)
; add sp,-16
; addi sp,sp,-16
; block0:
; andi a5,a2,63
; li a3,64
Expand All @@ -1992,11 +1992,11 @@ block0(v0: i128, v1: i128):
; li a4,64
; andi a2,a2,127
; select [a0,a1],[a3,a5],[s11,a3]##condition=(a2 uge a4)
; add sp,+16
; addi sp,sp,16
; ld s11,-8(sp)
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; addi sp,sp,16
; ret
;
; Disassembled:
Expand Down
4 changes: 2 additions & 2 deletions cranelift/filetests/filetests/isa/riscv64/call-indirect.clif
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,15 +10,15 @@ block0(v0: i64, v1: i64):
}

; VCode:
; add sp,-16
; addi sp,sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; block0:
; callind a1
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; addi sp,sp,16
; ret
;
; Disassembled:
Expand Down
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