[RWRoute] Add --lutRoutethru option #932

eddieh-xlnx · 2024-01-04T20:24:37Z

Add an option (disabled by default) that enables unused LUT resources to be routed through.

When LUT routethrus are enabled, optimizations added in #888 and #893 must be fully and partially disabled. Recall that these optimizations prevent input site pins (PINFEEDs) from being explored unless they're the target, and also prevent some more nodes that fanout to such input site pins when not in the vicinity of the target, respectively. For LUT routethrus to be considered, these optimizations must be fully/partially disabled, respectively.

Currently, this PR disables these optimizations across the entire device, meaning that all possible LUT routethrus in a connection's bounding box will be considered. A future optimization that may be beneficial would be to dynamically disable the #888 and #893 optimizations only in the vicinity of the source/sink tiles where routability is the most constrained.

Another intricacy is that the device model presents a number of routethru PIPs for each LUT; e.g. for the A LUT, there are 12 PIPs:

A[1-6] -> A_O
A[1-6] -> AMUX

One PIP for each of the 6 LUT inputs, crossed with one PIP for each SLICE output.
A limitation here appears to be that Vivado only allows one net to be routed through this LUT, meaning that you can't use A_O for one net and AMUX for another net by fracturing the LUT.

Thus, in this PR, only the A[1-6] -> A_O routethrus are considered, and all AMUX routethrus are discarded in order to guarantee that the LUT does not get fractured. A future optimization would be to emulate a PIP between A_O and AMUX so that both output nodes can still be considered for the same net.

Signed-off-by: Eddie Hung <[email protected]>

Since we expect sink RouteNode's to explicit set its type to be PINFEED_I Signed-off-by: Eddie Hung <[email protected]>

Signed-off-by: Eddie Hung <[email protected]>

Since their A and WA inputs are shared Signed-off-by: Eddie Hung <[email protected]>

Signed-off-by: Eddie Hung <[email protected]>

…hrus() Signed-off-by: Eddie Hung <[email protected]>

Signed-off-by: Eddie Hung <[email protected]>

…nns too" This reverts commit b049714. Signed-off-by: Eddie Hung <[email protected]> Conflicts: test/src/com/xilinx/rapidwright/design/tools/TestLUTTools.java

Signed-off-by: Eddie Hung <[email protected]>

Conflicts: src/com/xilinx/rapidwright/rwroute/RouteNodeGraph.java

Conflicts: src/com/xilinx/rapidwright/design/tools/LUTTools.java

eddieh-xlnx · 2024-01-08T17:32:29Z

In the same style of #895 and #888, here's a comparison on the benchmarks from the FPGA24 Routing Contest.

Before:

+--------------------------------+------+------------------+
| Benchmark                      | Pass | Wall Clock (sec) |
+--------------------------------+------+------------------+
| boom_med_pb_rwroute            | True |           262.08 |
| vtr_mcml_rwroute               | True |           279.52 |
| rosetta_fd_rwroute             | True |           196.19 |
| corundum_25g_rwroute           | True |           290.14 |
| vtr_lu64peeng_rwroute          | True |           272.99 |
| corescore_500_rwroute          | True |           185.01 |
| corescore_500_pb_rwroute       | True |           320.64 |
| mlcad_d181_lefttwo3rds_rwroute | True |          2042.37 |
| koios_dla_like_large_rwroute   | True |           466.00 |
| boom_soc_rwroute               | True |          1389.25 |
| ispd16_example2_rwroute        | True |           685.60 |
+--------------------------------+------+------------------+

Total: 6390 seconds.

After:

+--------------------------------+------+------------------+
| Benchmark                      | Pass | Wall Clock (sec) |
+--------------------------------+------+------------------+
| boom_med_pb_rwroute            | True |           294.62 |
| vtr_mcml_rwroute               | True |           364.77 |
| rosetta_fd_rwroute             | True |           222.55 |
| corundum_25g_rwroute           | True |           345.14 |
| vtr_lu64peeng_rwroute          | True |           323.03 |
| corescore_500_rwroute          | True |           215.31 |
| corescore_500_pb_rwroute       | True |           377.79 |
| mlcad_d181_lefttwo3rds_rwroute | True |          1193.92 |
| koios_dla_like_large_rwroute   | True |           549.58 |
| boom_soc_rwroute               | True |          1729.45 |
| ispd16_example2_rwroute        | True |           806.28 |
+--------------------------------+------+------------------+

Total: 6422 seconds (0.5% increase).

However, it looks like most benchmarks saw a small increase in runtime, except for mlcad_d181_lefttwo3rds_rwroute which had a massive halving.

And some statistics from TestRWRoute.testNonTimingDrivenFullRoutingWithGlobalNet():

Before:

Total wirelength:                       434815
Total INT tile nodes:                   837255
Total rnodes created:                  2860250
Average #children per node:                  4
------------------------------------------------------------------------------
Num iterations:                             14
Connections routed:                     374009
Nodes pushed:                        141263736
Nodes popped:                         65278765

After:

Total wirelength:                       399364
Total INT tile nodes:                   810400
Total rnodes created:                  3261557
Average #children per node:                  4
------------------------------------------------------------------------------
Num iterations:                             15
Connections routed:                     357638
Nodes pushed:                        211999922
Nodes popped:                        104715226

In terms of these RWRoute statistics, there is a noticeable wirelength saving, but a big increase in the nodes pushed/popped.

eddieh-xlnx · 2024-01-08T17:35:07Z

All in all, it looks like this option only improves runtime for one benchmark (but would be expected to reduce wirelength for all benchmarks) so it's not enabled by default.