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[RWRoute] Add "--lutPinSwapping" option #895

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merged 140 commits into from
Dec 1, 2023
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@eddieh-xlnx eddieh-xlnx commented Nov 25, 2023

Depends on:

When routing connections to LUT pins, this new --lutPinSwapping option causes all pins on that LUT to be considered as targets too. When only the x6LUT BEL is used, all A1-6 input pins can be used, but when x5LUT BEL is used only A1-5 can be.

Once routing is complete, LUTTools.swapLutPins() is called to commit the swaps into the design. This step can be deferred by setting the system property rapidwright.rwroute.lutPinSwapping.deferIntraSiteRoutingUpdates to true after which LUTTools.updateLutPinSwapsFromPIPs() is needed to bring the design back to a valid state.

Current limitations:

  • LUT pins that actually connect to other LUT cells (i.e. H6LUT.A[1-6] pins on SLICEM serve as the WA for all LUTs in that slice) are not allowed to be swapped (tracked by LUTTools.swapSingleLutPins() cannot swap H[1-6] when used as WA #901) -- bnn.dcp has an occurrence of this. To be clear -- H[1-6] that is not used as a WA for any other LUT [A-G] can still be swapped.
  • LOCK_PINS properties are not respected yet.

Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Including the reserved sink node on unrouted connections

Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
instead of .isExcluded()

Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Also update tests

Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
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As in #893 (comment), its "After" now serves as the "Before" here, on benchmarks from the FPGA24 Routing Contest:

Before:

+--------------------------------+------+------------------+
| Benchmark                      | Pass | Wall Clock (sec) |
+--------------------------------+------+------------------+
| boom_med_pb_rwroute            | True |           278.99 |
| vtr_mcml_rwroute               | True |           286.05 |
| rosetta_fd_rwroute             | True |           186.49 |
| corundum_25g_rwroute           | True |           304.22 |
| vtr_lu64peeng_rwroute          | True |           271.93 |
| corescore_500_rwroute          | True |           197.19 |
| corescore_500_pb_rwroute       | True |           324.17 |
| mlcad_d181_lefttwo3rds_rwroute | True |          1930.87 |
| koios_dla_like_large_rwroute   | True |           470.34 |
| boom_soc_rwroute               | True |          1463.28 |
| ispd16_example2_rwroute        | True |           677.40 |
+--------------------------------+------+------------------+

Total: 6391 seconds

After:

+--------------------------------+------+------------------+
| Benchmark                      | Pass | Wall Clock (sec) |
+--------------------------------+------+------------------+
| boom_med_pb_rwroute            | True |           186.17 |
| vtr_mcml_rwroute               | True |           373.80 |
| rosetta_fd_rwroute             | True |           178.20 |
| corundum_25g_rwroute           | True |           263.43 |
| vtr_lu64peeng_rwroute          | True |           283.86 |
| corescore_500_rwroute          | True |           191.60 |
| corescore_500_pb_rwroute       | True |           276.27 |
| mlcad_d181_lefttwo3rds_rwroute | True |           774.05 |
| koios_dla_like_large_rwroute   | True |           473.00 |
| boom_soc_rwroute               | True |          1689.49 |
| ispd16_example2_rwroute        | True |           574.04 |
+--------------------------------+------+------------------+

Total: 5264 seconds (18% reduction)

NOTE that not all designs show a saving:

  • vtr_mcml shows a 31% slowdown
  • vtr_lu64peeng shows a minor 4% slowdown
  • boom_soc shows a 15% slowdown

And some statistics from TestRWRoute.testNonTimingDrivenFullRoutingWithGlobalNet():

Before:

Total wirelength:                       434159
Total INT tile nodes:                   837457
Total rnodes created:                  2911761
Average #children per node:                  4
------------------------------------------------------------------------------
Num iterations:                             20
Connections routed:                     373779
Nodes pushed:                        148457301
Nodes popped:                         70444204

After:

Total wirelength:                       409536
Total INT tile nodes:                   799809
Total rnodes created:                  3018625
Average #children per node:                  4
------------------------------------------------------------------------------
Num iterations:                             23
Connections routed:                     370205
Nodes pushed:                        140693428
Nodes popped:                         71447770

@eddieh-xlnx eddieh-xlnx marked this pull request as ready for review November 30, 2023 22:16
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
@eddieh-xlnx eddieh-xlnx merged commit 7097956 into master Dec 1, 2023
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@eddieh-xlnx eddieh-xlnx deleted the rwroute_lutpinswap branch December 1, 2023 04:35
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2 participants