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22 Open 24 Closed
22 Open 24 Closed
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Issues list

钉钉讨论群二维码过期
#62 opened Mar 13, 2023 by smiling-boy-zixi
Readme information update
#61 opened Mar 12, 2023 by zhuanshulz
关于ip核配置
#60 opened Mar 9, 2023 by Jccando
synthesis failed
#59 opened Mar 5, 2023 by Strickland007
1
发现文档有个地方有错
#57 opened Mar 1, 2022 by landwolf
GPIO cannot clear interrupt
#56 opened Dec 30, 2021 by weils2021
1
Core is not modifiable
#53 opened Aug 30, 2021 by robtaylor
1
request for spec of hardware side
#44 opened Nov 26, 2019 by ray-mahong
5
开发文档的一些建议
#43 opened Nov 20, 2019 by springluo
1
为什么板子和群里的原理图对应不起来啊
#41 opened Nov 19, 2019 by ARC-MX
2
sync_fifo_16x16.fifo_thold VS doc.INTR_CTRL.RX_FIFO_TH
#39 opened Nov 18, 2019 by Jinfengyi
verilog的命名规则、缩写规范
#36 opened Nov 12, 2019 by 18271646571
语法错误
#35 opened Nov 12, 2019 by framsc
建议支持Yosys
#32 opened Nov 4, 2019 by RCoeurjoly
2
FPGA实现为什么要用synplify综合，全vivado流程有什么问题吗？
#27 opened Nov 1, 2019 by solvery
9
About Driver of CK-Linker for WIN10
#26 opened Oct 30, 2019 by curliph
1
If there is any doc describe the interface
#17 opened Oct 23, 2019 by daviesja
userguide p14，interrupt source description error
#16 opened Oct 23, 2019 by cmteric
Write_bitstream failed！
#15 opened Oct 23, 2019 by simux
2
哪里能看到设计文档？
#12 opened Oct 22, 2019 by solvery
1
突然想转行
#11 opened Oct 22, 2019 by WuxianDadao
6
about annotation
#7 opened Oct 21, 2019 by KingFrige
2
ProTip! Adding no:label will show everything without a label.