Simple UART transmitter and receiver
- You can freely specify the parameters that are baud rate, clock frequency and data width
- Interface are designed by VALID-READY handshake
- NOT supported parity bit
MIT
forked from medalotte/SystemVerilog-UART
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Simple UART transmitter and receiver
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SupunDK/SystemVerilog-UART
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- SystemVerilog 100.0%