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21 Open 39 Closed
21 Open 39 Closed
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Issues list

Document watch on uninitialized input signals.
#266 opened Oct 6, 2024 by Readon
SystemVerilog Support
#264 opened Aug 1, 2024 by digee-bytes
3
Document StreamAccessibleFifo and StreamShiftChain
#256 opened May 27, 2024 by Readon
@Readon
Add API description for HDElkDiagramGen
#206 opened Aug 15, 2023 by ZhaokunHu
simulator_specifics.rst: XSim is missing
#201 opened Jul 3, 2023 by dlmiles
Sequential logic/memory: matters arising from docs with annotations/blackbox/memory/device complexities
#196 opened Jun 15, 2023 by dlmiles
2
Document BU and BS string prefixes good first issue Good for newcomers
#159 opened Nov 30, 2022 by numero-744
Document SpinalSpec
#155 opened Nov 20, 2022 by numero-744
1 task
Suggestion of structure for docs
#151 opened Nov 18, 2022 by numero-744
@numero-744
26
equivalent constructs at elaboration time/hardware/sim
#145 opened Nov 16, 2022 by numero-744
@numero-744
5
Document randomize() returning new value
#141 opened Nov 14, 2022 by numero-744
Document implicit Fragment -> payload conversion
#140 opened Nov 10, 2022 by numero-744
3 tasks
Document switch(coverUnreachable = ...) good first issue Good for newcomers
#138 opened Nov 7, 2022 by numero-744
Document setWhen and clearWhen good first issue Good for newcomers
#137 opened Nov 3, 2022 by numero-744
5
Document Latch
#136 opened Nov 2, 2022 by numero-744
5
Add section for idioms
#131 opened Oct 24, 2022 by numero-744
@numero-744
7
Document mux limitation to 4096
#128 opened Oct 19, 2022 by numero-744
1 of 4 tasks
6
Document design error: Partially assigned register good first issue Good for newcomers
#127 opened Oct 18, 2022 by numero-744
Document PackedBundle
#124 opened Oct 15, 2022 by numero-744
Idea: automatically test examples
#123 opened Oct 13, 2022 by numero-744
3
update the bus_slave_factory
#87 opened Mar 31, 2022 by hanm2019
3
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