soc: st: stm32: stm32wbax: STM32WBA Cube 1.4.1 integration

Removed pure HAL stm32 functions not stricyly related to interrupt management Headers cleanup Signed-off-by: Alessandro Manganaro <[email protected]>
zephyrproject-rtos · Oct 24, 2024 · 3646af7 · 3646af7
1 parent fbd275d
commit 3646af7
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Showing 3 changed files with 3 additions and 58 deletions.
diff --git a/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c
@@ -4,22 +4,14 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/irq.h>
 #include <zephyr/kernel.h>
-#include <zephyr/arch/cpu.h>
-#include <zephyr/sys/util.h>
 #include <zephyr/drivers/entropy.h>
 #include <zephyr/logging/log.h>
-#include <cmsis_core.h>
-
-#include <linklayer_plat_local.h>
-
-#include <stm32_ll_pwr.h>
 
 #include "scm.h"
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
-LOG_MODULE_REGISTER(linklayer_plat);
+LOG_MODULE_REGISTER(linklayer_plat_adapt);
 
 #define RADIO_INTR_PRIO_HIGH_Z (RADIO_INTR_PRIO_HIGH + _IRQ_PRIO_OFFSET)
 #define RADIO_INTR_PRIO_LOW_Z (RADIO_INTR_PRIO_LOW + _IRQ_PRIO_OFFSET)
@@ -42,46 +34,12 @@ volatile uint32_t local_basepri_value;
 /* Radio SW low ISR global variable */
 volatile uint8_t radio_sw_low_isr_is_running_high_prio;
 
-void LINKLAYER_PLAT_ClockInit(void)
-{
-	LL_PWR_EnableBkUpAccess();
-
-	/* Select LSE as Sleep CLK */
-	__HAL_RCC_RADIOSLPTIM_CONFIG(RCC_RADIOSTCLKSOURCE_LSE);
-
-	LL_PWR_DisableBkUpAccess();
-
-	/* Enable AHB5ENR peripheral clock (bus CLK) */
-	__HAL_RCC_RADIO_CLK_ENABLE();
-}
 
 void LINKLAYER_PLAT_DelayUs(uint32_t delay)
 {
 	k_busy_wait(delay);
 }
 
-void LINKLAYER_PLAT_WaitHclkRdy(void)
-{
-	while (HAL_RCCEx_GetRadioBusClockReadiness() != RCC_RADIO_BUS_CLOCK_READY) {
-	}
-}
-
-void LINKLAYER_PLAT_AclkCtrl(uint8_t enable)
-{
-	LOG_DBG("enable: %d", enable);
-	if (enable) {
-		/* Enable RADIO baseband clock (active CLK) */
-		HAL_RCCEx_EnableRadioBBClock();
-
-		/* Polling on HSE32 activation */
-		while (LL_RCC_HSE_IsReady() == 0) {
-		}
-	} else {
-		/* Disable RADIO baseband clock (active CLK) */
-		HAL_RCCEx_DisableRadioBBClock();
-	}
-}
-
 void LINKLAYER_PLAT_GetRNG(uint8_t *ptr_rnd, uint32_t len)
 {
 	int ret;
@@ -207,11 +165,6 @@ void LINKLAYER_PLAT_DisableIRQ(void)
 	irq_counter++;
 }
 
-void LINKLAYER_PLAT_Assert(uint8_t condition)
-{
-	__ASSERT_NO_MSG(condition);
-}
-
 void LINKLAYER_PLAT_EnableSpecificIRQ(uint8_t isr_type)
 {
 

diff --git a/soc/st/stm32/stm32wbax/hci_if/ll_sys_if_adapt.c b/soc/st/stm32/stm32wbax/hci_if/ll_sys_if_adapt.c
@@ -8,12 +8,9 @@
 
 #include <zephyr/logging/log.h>
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
-LOG_MODULE_REGISTER(ll_sys_if);
+LOG_MODULE_REGISTER(ll_sys_if_adapt);
 
-#include "ll_intf.h"
 #include "ll_sys.h"
-#include "linklayer_plat.h"
-#include "app_conf.h"
 
 extern struct k_mutex ble_ctlr_stack_mutex;
 extern struct k_work_q ll_work_q;
@@ -40,8 +37,3 @@ void ll_sys_bg_process_init(void)
 {
 	k_work_init(&ll_sys_work, &ll_sys_bg_process_handler);
 }
-
-void ll_sys_config_params(void)
-{
-	ll_intf_config_ll_ctx_params(USE_RADIO_LOW_ISR, NEXT_EVENT_SCHEDULING_FROM_ISR);
-}
diff --git a/west.yml b/west.yml
@@ -233,7 +233,7 @@ manifest:
       groups:
         - hal
     - name: hal_stm32
-      revision: 6f0e5f70cb540c487e3e3678af2e95d0937f9863
+      revision: pull/237/head
       path: modules/hal/stm32
       groups:
         - hal