s32: s32ze: patch QSPI for integration with zephyr

Adapt macros that are used in the QSPI memc and QSPI flash shim drivers. Signed-off-by: Cong Nguyen Huu <[email protected]>
zephyrproject-rtos · Oct 21, 2024 · 397aa1a · 397aa1a
1 parent 652fee9
commit 397aa1a
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Showing 4 changed files with 9 additions and 8 deletions.
diff --git a/s32/drivers/s32ze/BaseNXP/header/S32Z2_QUADSPI.h b/s32/drivers/s32ze/BaseNXP/header/S32Z2_QUADSPI.h
@@ -71,8 +71,8 @@
 /** QuadSPI - Size of Registers Arrays */
 #define QuadSPI_RBDR_COUNT                        64u
 #define QuadSPI_LUT_COUNT                         80u
-#define QuadSPI_FRAD_COUNT                        8u
-#define QuadSPI_MDAD_COUNT                        2u
+#define QuadSPI_FRAD_COUNT                        8
+#define QuadSPI_MDAD_COUNT                        2
 
 /** QuadSPI - Register Layout Typedef */
 typedef struct {

diff --git a/s32/drivers/s32ze/Mem_EXFLS/include/Qspi_Ip_Types.h b/s32/drivers/s32ze/Mem_EXFLS/include/Qspi_Ip_Types.h
@@ -121,7 +121,7 @@ extern "C"{
 #define QSPI_IP_ERASE_TYPES                 (4U)
 
 /*! @brief Number of AHB buffers in the device */
-#define QSPI_IP_AHB_BUFFERS                 (4U)
+#define QSPI_IP_AHB_BUFFERS                 4
 
 /*! Invalid index in virtual LUT, used for unsupported features */
 #define QSPI_IP_LUT_INVALID                 (uint16)0xFFFFU

diff --git a/s32/soc/s32z270/include/Qspi_Ip_Cfg.h b/s32/soc/s32z270/include/Qspi_Ip_Cfg.h
@@ -28,7 +28,7 @@ extern "C"{
 * 3) internal and external interfaces from this unit
 ==================================================================================================*/
 #include "Qspi_Ip_Types.h"
-
+#include <zephyr/devicetree.h>
 
 /*==================================================================================================
 *                              SOURCE FILE VERSION INFORMATION
@@ -51,7 +51,7 @@ extern "C"{
 ==================================================================================================*/
 
 /* Number of serial flash devices */
-#define QSPI_IP_MEM_INSTANCE_COUNT        (1U)
+#define QSPI_IP_MEM_INSTANCE_COUNT        DT_NUM_INST_STATUS_OKAY(nxp_s32_qspi_hyperflash)
 
 /* Maximum number of retries for Write Enable command */
 #define QSPI_IP_MAX_RETRY                 (3U)

diff --git a/s32/soc/s32z270/include/Qspi_Ip_CfgDefines.h b/s32/soc/s32z270/include/Qspi_Ip_CfgDefines.h
@@ -27,6 +27,7 @@ extern "C"{
 * 2) needed interfaces from external units
 * 3) internal and external interfaces from this unit
 ==================================================================================================*/
+#include <zephyr/devicetree.h>
 
 /*==================================================================================================
 *                              SOURCE FILE VERSION INFORMATION
@@ -48,9 +49,9 @@ extern "C"{
 ==================================================================================================*/
 
 
-#define QSPI_IP_SFP_ENABLE_GLOBAL                    (STD_ON)
-#define QSPI_IP_SFP_ENABLE_MDAD                      (STD_ON)
-#define QSPI_IP_SFP_ENABLE_FRAD                      (STD_ON)
+#define QSPI_IP_SFP_ENABLE_MDAD   DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_qspi_sfp_mdad)
+#define QSPI_IP_SFP_ENABLE_FRAD   DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_qspi_sfp_frad)
+#define QSPI_IP_SFP_ENABLE_GLOBAL UTIL_OR(QSPI_IP_SFP_ENABLE_MDAD, QSPI_IP_SFP_ENABLE_FRAD)		
 
 
 /* Enable Multicore support when using MemAcc*/