Upgrade x86_64 to Master

Signed-off-by: liwenxiang1 <[email protected]>

arch/x86_64/include/hpet.h

@@ -45,10 +45,10 @@
 #  define HPET_GCAPID_REVID_MASK    (0xfful << HPET_GCAPID_REVID_SHIFT)
 #define HPET_GCAPID_NUMTIM_SHIFT    (8ul)     /* Bits 8-12: Number of Timers */
 #define HPET_GCAPID_NUMTIM_MASK     (0x1ful << HPET_GCAPID_NUMTIM_SHIFT)
-#define HPET_GCAPID_COUNTSIZE       (1 << 13) /* Bit 13: Counter size, 0: 32 bit, 1: 64 bit */
+#define HPET_GCAPID_COUNTSIZE       (1 << 13) /* Bit 13: Conter size, 0: 32 bit, 1: 64 bit */
                                               /* Bit 14: Reserved */
 #define HPET_GCAPID_LEGROUTE        (1 << 15) /* Bit 15: LegacyReplacement Route Capable */
-#define HPET_GCAPID_VENDORID_SHIFT  (16ul)    /* Bits 16-31: Vendor ID */
+#define HPET_GCAPID_VENDORID_SHIFT  (16ul)    /* Bits 16-31: Ventor ID */
 #  define HPET_GCAPID_VENDORID_MASK (0x7ffful << HPET_GCAPID_VENDORID_SHIFT)
 #define HPET_GCAPID_CLKPER_SHIFT    (32ul)    /* Bits 32-63: Main Counter Tick Period in ps */
 #  define HPET_GCAPID_CLKPER_MASK   (0x7ffffffful << HPET_GCAPID_CLKPER_SHIFT)
@@ -68,7 +68,7 @@
 #define HPET_TCONF_INTTYPE          (1 << 1) /* Bit 1: Timer n Interrupt Type (0: edge, 1: level) */
 #define HPET_TCONF_INTEN            (1 << 2) /* Bit 2: Timer n Interrupt Enable */
 #define HPET_TCONF_TYPE             (1 << 3) /* Bit 3: Timer n Type (0: non-periodic, 1: periodic) */
-#define HPET_TCONF_PERCAP           (1 << 4) /* Bit 4: Timer n Periodic Interrupt Capable */
+#define HPET_TCONF_PERCAP           (1 << 4) /* Bit 4: Timer n Periodic Interupt Capable */
 #define HPET_TCONF_SIZECAP          (1 << 5) /* Bit 5: Timer n Size */
 #define HPET_TCONF_VALSET           (1 << 6) /* Bit 6: Timer n Value Set */
                                              /* Bit 7: Reserved */

arch/x86_64/include/intel64/arch.h

@@ -208,6 +208,8 @@
 #  define X86_64_CPUID_07_AVX512VL    (1 << 31)
 #define X86_64_CPUID_XSAVE            0x0d
 #define X86_64_CPUID_TSC              0x15
+#define X86_64_CPUID_EXTINFO          0x80000001
+#  define X86_64_CPUID_EXTINFO_RDTSCP (1 << 27)
 
 /* MSR Definitions */
 
@@ -275,7 +277,7 @@
 #  define MSR_X2APIC_ICR_OTHERS        0x000c0000  /* Send to all APICs, excluding self. */
 #  define MSR_X2APIC_ICR_BUSY          0x00001000
 #  define MSR_X2APIC_ICR_FIXED         0x00000000
-#  define MSR_X2APIC_DESTINATION(d)    ((d) << 32)
+#  define MSR_X2APIC_DESTINATION(d)    ((d) << 32ul)
 #define MSR_X2APIC_LVTT         0x832
 #  define MSR_X2APIC_LVTT_X1           0x0000000B  /* divide counts by 1 */
 #  define MSR_X2APIC_LVTT_PERIODIC     0x00020000  /* Periodic */
@@ -466,7 +468,7 @@ begin_packed_struct struct ist_s
 
 begin_packed_struct struct tss_s
 {
-  struct ist_s  ist;    /* IST  */
+  struct ist_s ist;     /* IST  */
   void         *cpu;    /* CPU private data */
 } end_packed_struct;
 

arch/x86_64/include/intel64/irq.h

@@ -461,6 +461,10 @@
 
 #define XMMAREA_REGS     (25)
 
+/* Aux register used by implementation */
+
+#define REG_AUX          (26 + XMMAREA_REG_OFFSET)
+
 /* NOTE 2: This is not really state data.  Rather, this is just a convenient
  *   way to pass parameters from the interrupt handler to C code.
  */
@@ -478,6 +482,10 @@
 #define XCP_ALIGN_DOWN(a) ((a) & ~XCP_ALIGN_MASK)
 #define XCP_ALIGN_UP(a)   (((a) + XCP_ALIGN_MASK) & ~XCP_ALIGN_MASK)
 
+/* Aux register flags */
+
+#define REG_AUX_FULLCONTEXT (1 << 0) /* Force full context switch */
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/

arch/x86_64/include/irq.h

@@ -50,6 +50,7 @@
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
+
 /* CPU private data */
 
 struct intel64_cpu_s

arch/x86_64/include/setjmp.h

@@ -0,0 +1,106 @@
+/****************************************************************************
+ * arch/x86_64/include/setjmp.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_X86_64_INCLUDE_SETJUMP_H
+#define __ARCH_X86_64_INCLUDE_SETJUMP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+  /* Storage order: %rbx, %rsp, %rbp, %r12, %r13, %r14, %r15, %rip */
+
+#  define XCPTCONTEXT_REGS    9
+#  define XCPTCONTEXT_SIZE    (8 * XCPTCONTEXT_REGS)
+
+#  ifdef __ASSEMBLY__
+
+#    define JB_RBX            (0*8)
+#    define JB_RSP            (1*8)
+#    define JB_RBP            (2*8)
+#    define JB_R12            (3*8)
+#    define JB_R13            (4*8)
+#    define JB_R14            (5*8)
+#    define JB_R15            (6*8)
+#    define JB_RIP            (7*8)
+#    define JB_FLAG           (8*8)
+
+#  else
+
+#    define JB_RBX            (0)
+#    define JB_RSP            (1)
+#    define JB_RBP            (2)
+#    define JB_R12            (3)
+#    define JB_R13            (4)
+#    define JB_R14            (5)
+#    define JB_R15            (6)
+#    define JB_RIP            (7)
+#    define JB_FLAG           (8)
+
+#  endif /* __ASSEMBLY__ */
+
+/* Compatibility definitions */
+
+#  define JB_FP               JB_RBP
+#  define JB_SP               JB_RSP
+#  define JB_PC               JB_RIP
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long xcpt_reg_t;
+typedef xcpt_reg_t jmp_buf[XCPTCONTEXT_REGS];
+
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+int setjmp(jmp_buf env);
+void longjmp(jmp_buf env, int val) noreturn_function;
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* __ARCH_X86_64_INCLUDE_SETJUMP_H */

arch/x86_64/src/Makefile

@@ -97,6 +97,10 @@ ifeq ($(CONFIG_LIBSUPCXX),y)
   EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a}}
 endif
 
+ifeq ($(CONFIG_CXX_EXCEPTION),y)
+  EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libgcc_eh.a}}
+endif
+
 VPATH = chip:common:$(ARCH_SUBDIR)
 
 all: libarch$(LIBEXT)

arch/x86_64/src/common/CMakeLists.txt

@@ -23,16 +23,18 @@ set(SRCS
     x86_64_copystate.c
     x86_64_exit.c
     x86_64_getintstack.c
-    x86_64_mdelay.c
     x86_64_initialize.c
     x86_64_modifyreg8.c
     x86_64_modifyreg16.c
     x86_64_modifyreg32.c
     x86_64_nputs.c
     x86_64_switchcontext.c
-    x86_64_udelay.c
     x86_64_tcbinfo.c)
 
+if(CONFIG_ARCH_HAVE_FORK)
+  list(APPEND SRCS x86_64_fork.c fork.S)
+endif()
+
 if(CONFIG_PCI)
   list(APPEND SRCS x86_64_pci.c)
 endif()
@@ -41,6 +43,10 @@ if(CONFIG_ARCH_X86_64_ACPI)
   list(APPEND SRCS x86_64_acpi.c)
 endif()
 
+if(CONFIG_SCHED_THREAD_LOCAL)
+  list(APPEND SRCS x86_64_tls.c)
+endif()
+
 if(CONFIG_ARCH_USE_MMU)
   list(APPEND SRCS x86_64_mmu.c)
 endif()
@@ -49,4 +55,8 @@ if(CONFIG_ARCH_ADDRENV)
   list(APPEND SRCS x86_64_addrenv.c x86_64_addrenv_perms.c)
 endif()
 
+if(NOT CONFIG_ALARM_ARCH)
+  list(APPEND SRCS x86_64_udelay.c x86_64_mdelay.c)
+endif()
+
 target_sources(arch PRIVATE ${SRCS})

arch/x86_64/src/common/Make.defs

@@ -18,12 +18,17 @@
 #
 ############################################################################
 
-# Common x86_64 files
+# Common x86_64 and intel64 files
 
 CMN_CSRCS += x86_64_allocateheap.c x86_64_copystate.c x86_64_exit.c
-CMN_CSRCS += x86_64_getintstack.c x86_64_mdelay.c x86_64_initialize.c
+CMN_CSRCS += x86_64_getintstack.c  x86_64_initialize.c x86_64_nputs.c
 CMN_CSRCS += x86_64_modifyreg8.c x86_64_modifyreg16.c x86_64_modifyreg32.c
-CMN_CSRCS += x86_64_nputs.c x86_64_switchcontext.c x86_64_udelay.c
+CMN_CSRCS += x86_64_switchcontext.c
+
+ifeq ($(CONFIG_ARCH_HAVE_FORK),y)
+CMN_CSRCS += x86_64_fork.c
+CMN_ASRCS += fork.S
+endif
 
 ifeq ($(CONFIG_PCI),y)
 CMN_CSRCS += x86_64_pci.c
@@ -33,10 +38,18 @@ ifeq ($(CONFIG_ARCH_X86_64_ACPI),y)
 CMN_CSRCS += x86_64_acpi.c
 endif
 
+ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
+CMN_CSRCS += x86_64_tls.c
+endif
+
 ifeq ($(CONFIG_ARCH_USE_MMU),y)
 CMN_CSRCS += x86_64_mmu.c
 endif
 
 ifeq ($(CONFIG_ARCH_ADDRENV),y)
 CMN_CSRCS += x86_64_addrenv.c x86_64_addrenv_perms.c
 endif
+
+ifndef CONFIG_ALARM_ARCH
+CMN_CSRCS += x86_64_udelay.c x86_64_mdelay.c
+endif