Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Added Xilinx UltraScale+ MPSoC CSU Support CSU support #545

Draft
wants to merge 1 commit into
base: master
Choose a base branch
from

Conversation

dgarske
Copy link
Contributor

@dgarske dgarske commented Jan 31, 2025

Added Xilinx UltraScale+ MPSoC CSU Support CSU support.
Enabled support for offloading SHA3 hashing to CSU hardware using PKA=1.
Added support for enabling JTAG at runtime if CSU_DEBUG is set. Requires patching PMUFW to enable register access. See: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2587197506/Zynq+UltraScale+MPSoC+JTAG+Enable+in+U-Boot

@dgarske dgarske self-assigned this Jan 31, 2025
Enabled support for offloading SHA3 hashing to CSU hardware using PKA=1.
Added support for enabling JTAG at runtime if CSU_DEBUG is set. Requires patching PMUFW to enable register access. See: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2587197506/Zynq+UltraScale+MPSoC+JTAG+Enable+in+U-Boot
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant