Skip to content

Actions: wiredlab/chip-design-tt10-verilog-template

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
9 workflow runs
9 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

update top module name gds #3: Commit 7336386 pushed by obliviouX
February 3, 2025 04:29 29s main
main
February 3, 2025 04:29 29s
update top module name docs #3: Commit 7336386 pushed by obliviouX
February 3, 2025 04:29 2m 7s main
main
February 3, 2025 04:29 2m 7s
update top module name test #3: Commit 7336386 pushed by obliviouX
February 3, 2025 04:29 39s main
main
February 3, 2025 04:29 39s
test commit test #2: Commit 6dd123b pushed by obliviouX
January 28, 2025 18:52 36s main
main
January 28, 2025 18:52 36s
test commit gds #2: Commit 6dd123b pushed by obliviouX
January 28, 2025 18:52 35s main
main
January 28, 2025 18:52 35s
test commit docs #2: Commit 6dd123b pushed by obliviouX
January 28, 2025 18:52 2m 3s main
main
January 28, 2025 18:52 2m 3s
Initial commit gds #1: Commit 67724bd pushed by obliviouX
January 22, 2025 00:22 51s main
main
January 22, 2025 00:22 51s
Initial commit test #1: Commit 67724bd pushed by obliviouX
January 22, 2025 00:22 19h 39m 21s main
main
January 22, 2025 00:22 19h 39m 21s
Initial commit docs #1: Commit 67724bd pushed by obliviouX
January 22, 2025 00:22 1d 5h 21m 23s main
main
January 22, 2025 00:22 1d 5h 21m 23s