Skip to content

Issues: verilog-to-routing/vtr-verilog-to-routing

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

426 Open 600 Closed
426 Open 600 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Wire lookahead runtime scales poorly with number of switch/segment types
#2811 opened Nov 15, 2024 by petergrossmann21
Update benchmark page descriptions for VTR 9 release
#2810 opened Nov 15, 2024 by vaughnbetz
@vaughnbetz
SDC Parsing causes assertion error for specific netlist sweeping option combination
#2809 opened Nov 15, 2024 by petergrossmann21
Troubleshooting RR graphs with poor router performance
#2803 opened Nov 7, 2024 by petergrossmann21
4
Comparing performance/quality trade-off of SPEC and VTR random number generators.
#2798 opened Nov 3, 2024 by soheilshahrouz
@soheilshahrouz
[Prepacker] Pack Molecule Data Structure Clarity
#2791 opened Oct 30, 2024 by AlexandreSinger
1 of 9 tasks
Change in path from input to output place file causes digest error.
#2783 opened Oct 18, 2024 by petergrossmann21
Optimize run time and memory footprint to build the choke point data structures in routing
#2782 opened Oct 18, 2024 by vaughnbetz
@amin1377
Issue with Molecule Clustering Causing Suboptimal Placement
#2775 opened Oct 16, 2024 by WindFrank
Unexpected High Gain Causes Unrelated Blocks to Be Added to Clusters
#2763 opened Oct 10, 2024 by WindFrank
VPR error when trying to compile my design generated using PRGA
#2760 opened Oct 5, 2024 by polarbearsrock
Turn on choke point analysis in the router by default, and make help etc. more user-friendly
#2750 opened Sep 27, 2024 by vaughnbetz
5 tasks
@amin1377
2
Overly Verbose Router Look ahead warnings
#2748 opened Sep 25, 2024 by ZohairZaidi
Add visualization for flat routing in the VPR graphics
#2740 opened Sep 21, 2024 by vaughnbetz
1
[IntraClusterPlacement] Code Cleanups
#2732 opened Sep 20, 2024 by AlexandreSinger
1 of 4 tasks
2
[Packer] Load The ClusteredNetlist Directly From The ClusterLegalizer VPR VPR FPGA Placement & Routing Tool
#2731 opened Sep 20, 2024 by AlexandreSinger
[ClusterLegalizer] Code Cleanups VPR VPR FPGA Placement & Routing Tool
#2730 opened Sep 20, 2024 by AlexandreSinger
6 tasks
[Packer] Setting Higher Target Pin Utilization When Regions are Full VPR VPR FPGA Placement & Routing Tool
#2729 opened Sep 20, 2024 by AlexandreSinger
CLBs Positioned Far from IOs
#2727 opened Sep 17, 2024 by WindFrank
Packing Devices from Two Separate Parts of a Netlist into a Single CLB
#2726 opened Sep 17, 2024 by WindFrank
1
Improve 3D switch block commenting and move command line option to arch file
#2722 opened Sep 13, 2024 by vaughnbetz
3 tasks
VTR seems to struggle with being smart about how it packs into memories
#2718 opened Sep 12, 2024 by WhiteNinjaZ
Multibit Adder Architecture Failure
#2717 opened Sep 9, 2024 by shrekliao
VTR throws warning for shorted SB connections
#2712 opened Sep 4, 2024 by WhiteNinjaZ
@WhiteNinjaZ
Issue with Multibit Adder in VTR flagship architecture
#2710 opened Sep 3, 2024 by shrekliao
ProTip! Adding no:label will show everything without a label.