Uplift dram and l1 allocators to use dram/l1 specific alignment #17122
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…_noc_coord_descriptor
…rm_with_block_sharded_v2_8x8_grid
…name for l1 alignment
llongTT
requested review from
razorback3,
dongjin-na,
bbradelTT,
yugaoTT,
tt-aho,
asandhupatlaTT,
ntarafdar,
sjameelTT,
jaykru-tt,
yugi957,
jvegaTT,
nardoTT,
aliuTT,
tt-asaigal,
omilyutin-tt,
abhullar-tt,
pgkeller,
tt-dma,
ubcheema and
davorchap
as code owners
bbradelTT
approved these changes
Jan 27, 2025
| @@ -1061,7 +1061,7 @@ conv_op_l1_usage conv2d::calculate_L1_usage( | |||
| } else if (output_dtype == DataType::FLOAT32) { | |||
| per_core_out_width_aligned *= 4; | |||
| } | |||
| output_size = round_up(per_core_out_width_aligned, 32) * pconfig.per_core_out_matrix_height; | |||
| output_size = round_up(per_core_out_width_aligned, 16) * pconfig.per_core_out_matrix_height; | |||
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It would be nice to have defines/constexpr for these magic numbers (16 in this case, 32 before).
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if this is a function just used for L1 we can use HAL api: get_alignment(HalMemType::L1)
sankarmanoj-tt
approved these changes
Jan 27, 2025
esmalTT
reviewed
Jan 27, 2025
| @@ -108,7 +108,7 @@ def test_unet_trace( | |||
|
|
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| @skip_for_grayskull("UNet not currently supported on GS") | |||
| @pytest.mark.parametrize( | |||
| "device_params", [{"l1_small_size": 68864, "trace_region_size": 442368, "num_command_queues": 2}], indirect=True | |||
| "device_params", [{"l1_small_size": 68864, "trace_region_size": 917504, "num_command_queues": 2}], indirect=True | |||
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Why so much larger? Seems odd we now need to double the trace region size.
| @@ -343,7 +343,7 @@ def test_unet_trace_2cq_multi_device( | |||
|
|
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| @skip_for_grayskull("UNet not currently supported on GS") | |||
| @pytest.mark.parametrize( | |||
| "device_params", [{"l1_small_size": 68864, "trace_region_size": 424960, "num_command_queues": 2}], indirect=True | |||
| "device_params", [{"l1_small_size": 68864, "trace_region_size": 1376256, "num_command_queues": 2}], indirect=True | |||
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Same here - why such a large increase?
ntarafdar
approved these changes
Jan 27, 2025
yugaoTT
approved these changes
Jan 27, 2025
tt-aho
approved these changes
Jan 27, 2025
| @@ -1164,7 +1164,7 @@ conv_op_l1_usage conv2d::calculate_L1_usage( | |||
| } else if (output_dtype == DataType::FLOAT32) { | |||
| per_core_out_width_aligned *= 4; | |||
| } | |||
| output_size = round_up(per_core_out_width_aligned, 32) * pconfig.per_core_out_matrix_height; | |||
| output_size = round_up(per_core_out_width_aligned, 16) * pconfig.per_core_out_matrix_height; | |||
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Should also not be hardcoded to 16
Comment on lines
+174
to
+175
| uint32_t l1_alignment = tt::tt_metal::hal.get_alignment(tt::tt_metal::HalMemType::L1); | ||
| uint32_t per_core_N_bytes_padded = tt::round_up(per_core_N * datum_size_bytes, l1_alignment); |
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Would it make more sense to query a's buffer alignment here instead of querying the hal?
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Ticket
#13609
Problem description
Using the max of DRAM and L1 alignment for both DRAM and L1 buffers was causing pcc mismatches in i2s and s2i.
What's changed
Use L1/DRAM specific alignment for respective allocations. This will require some ops to be uplifted to handle re-alignment
Checklist