[sw/common] Cleanup central makefile and linker script (#1077)

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 26.10.2024 | 1.10.5.11 | cleanup central makefile and linker script | [#1077](https://github.com/stnolting/neorv32/pull/1077) |
 | 21.10.2024 | 1.10.5.10 | :test_tube: rework linker script's ROM/IMEM default size (=16kB); add customization variable to all makefiles in `sw/example` | [#1072](https://github.com/stnolting/neorv32/pull/1072) |
 | 20.10.2024 | 1.10.5.9 | :warning: rework XIRQ controller; remove "interrupt pending" register `EIP` | [#1071](https://github.com/stnolting/neorv32/pull/1071) |
 | 18.10.2024 | 1.10.5.8 | minor RTL code cleanups | [#1068](https://github.com/stnolting/neorv32/pull/1068) |

docs/datasheet/cpu.adoc

@@ -531,6 +531,7 @@ The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.
 |=======================
 | Class | Instructions | Execution cycles
 | ALU           | `add[i]` `slt[i]` `slt[i]u` `xor[i]` `or[i]` `and[i]` `sub` `lui` `auipc` | 2
+| No-operation  | "`nop`"                                                                   | 2
 | ALU shifts    | `sll[i]` `srl[i]` `sra[i]`                                                | 3 + 1..32; FAST_SHIFT: 4
 | Branches      | `beq` `bne` `blt` `bge` `bltu` `bgeu`                                     | taken: 6; not taken: 3
 | Jump/call     | `jal[r]`                                                                  | 6

docs/datasheet/rationale.adoc

@@ -86,17 +86,17 @@ single-cycle and fully-pipelined designs: they provide higher throughput and clo
 single-cycle counterparts while having less hardware complexity (= area) then a fully-pipelined designs. I decided to
 use the multi-cycle approach because of the following reasons:
 
-* Multi-cycle architecture are quite small! There is no need for pipeline hazard detection and resolution logic
-(e.g. forwarding). Furthermore, you can "re-use" parts of the core to do several tasks (e.g. the ALU is used for the
-actual data processing, but also for address generation, branch condition check and branch target computation).
+* Multi-cycle architectures are quite small! There is no need for pipeline hazard detection/resolution logic
+(e.g. forwarding). Furthermore, you can "re-use" parts of the core to do several tasks (e.g. the ALU is used for
+actual data processing and also for address generation, branch condition check and branch target computation).
 * Single-cycle architectures require memories that can be read asynchronously - a thing that is not feasible to implement
-in real world applications (i.e. FPGA block RAM is entirely synchronous). Furthermore, such design usually have a very
+in real-world applications (i.e. FPGA block RAM is entirely synchronous). Furthermore, such designs usually have a very
 long critical path tremendously reducing maximal operating frequency.
 * Pipelined designs increase performance by having several instruction "in fly" at the same time. But this also means
 there is some kind of "out-of-order" behavior: if an instruction at the end of the pipeline causes an exception
-all the instructions in earlier stages have to be invalidated. Potential architecture state changes have to be made _undone_
+all the instructions in earlier stages have to be invalidated. Potential architectureral state changes have to be made _undone_
 requiring additional (exception-handling) logic. In a multi-cycle architecture this situation cannot occur since only a
-single instruction is being processed at a time.
+single instruction is being processed ("in-fly") at a time.
 * Having only a single instruction in fly does not only reduce hardware costs, it also simplifies
 simulation/verification/debugging, state preservation/restoring during exceptions and extensibility (no need to care
 about pipeline hazards) - but of course at the cost of reduced throughput.
@@ -109,7 +109,7 @@ exceptions).
 
 
 [discrete]
-==== Design Goals
+==== Objective
 
 [start=1]
 . RISC-V-compliance and -compatibility

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100510"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100511"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

sw/bootloader/makefile

@@ -1,4 +1,23 @@
-# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
+# Bootloader (for BOOTROM) makefile.
+
+# Minimal RISC-V ISA only
+MARCH = rv32i_zicsr_zifencei
+
+# Optimize for minimal size
+EFFORT = -Os
+
+# Adjust memory size and base for BOOTROM
+# Define MAKE_BOOTLOADER for SW library (reduces footprint)
+# Enable link-time-optimization
+USER_FLAGS += \
+-Wl,--defsym,__neorv32_rom_size=4k \
+-Wl,--defsym,__neorv32_rom_base=0xFFFFC000 \
+-Wl,--defsym,__neorv32_ram_size=512 \
+-DMAKE_BOOTLOADER \
+-flto
+
+# Set path to NEORV32 root directory
 NEORV32_HOME ?= ../..
 
+# Include the main NEORV32 makefile
 include $(NEORV32_HOME)/sw/common/common.mk

sw/common/common.mk

@@ -1,6 +1,8 @@
 # ================================================================================ #
 # NEORV32 Application Software Makefile                                            #
 # -------------------------------------------------------------------------------- #
+# Do not edit this file! Use the re-defines in the project-local makefile instead. #
+# -------------------------------------------------------------------------------- #
 # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              #
 # Copyright (c) NEORV32 contributors.                                              #
 # Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  #
@@ -9,8 +11,8 @@
 # ================================================================================ #
 
 # -----------------------------------------------------------------------------
-# Default configuration (do not edit this file; override the configuration
-# when including this Makefile in the project-specific Makefile)
+# Default configuration (DO NOT EDIT THIS FILE! REDEFINE / OVERRIDE THE DEFAULT
+# CONFIGURATION WHEN INCLUDING THIS MAKEFILE IN THE PROJECT-SPECIFIC MAKEFILE)
 # -----------------------------------------------------------------------------
 # User's application sources (*.c, *.cpp, *.s, *.S); add additional files here
 APP_SRC ?= $(wildcard ./*.c) $(wildcard ./*.s) $(wildcard ./*.cpp) $(wildcard ./*.S)
@@ -106,7 +108,7 @@ IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
 # Compiler & linker flags
 CC_OPTS  = -march=$(MARCH) -mabi=$(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
-CC_OPTS += -mstrict-align -mbranch-cost=10 -Wl,--gc-sections -ffp-contract=off
+CC_OPTS += -mstrict-align -mbranch-cost=10 -Wl,--gc-sections -ffp-contract=off -g
 CC_OPTS += $(USER_FLAGS)
 LD_LIBS =  -lm -lc -lgcc
 LD_LIBS += $(USER_LIBS)
@@ -127,7 +129,7 @@ NEO_ASFLAGS = $(CC_FLAGS) $(ASFLAGS)
 # -----------------------------------------------------------------------------
 # Application output definitions
 # -----------------------------------------------------------------------------
-.PHONY: check info help elf_info clean clean_all bootloader
+.PHONY: check info help elf_info clean clean_all
 .DEFAULT_GOAL := help
 
 asm:     $(APP_ASM)
@@ -142,12 +144,6 @@ image:   $(APP_VHD)
 install: image install-$(APP_VHD)
 all:     $(APP_ASM) $(APP_EXE) $(APP_HEX) $(APP_BIN) $(APP_COE) $(APP_MEM) $(APP_MIF) $(APP_VHD) install hex bin
 
-# Check if making bootloader
-# Use different base address and length for instruction memory/"rom" (BOOTROM instead of IMEM)
-# Also define "MAKE_BOOTLOADER" symbol for simplified code when building the bootloader
-# Use link-time optimization to further shrink bootloader code size
-target bootloader | bl_image: CC_OPTS += -Wl,--defsym=MAKE_BOOTLOADER=1 -DMAKE_BOOTLOADER -flto
-
 # -----------------------------------------------------------------------------
 # Image generator targets
 # -----------------------------------------------------------------------------
@@ -240,25 +236,19 @@ $(APP_MEM): main.bin $(IMAGE_GEN)
 	@$(IMAGE_GEN) -raw_mem $< $@ $(shell basename $(CURDIR))
 
 # -----------------------------------------------------------------------------
-# Boot image targets
+# BOOTROM / booloader image targets
 # -----------------------------------------------------------------------------
-# Create VHDL boot image
-$(BOOT_VHD): main.bin $(IMAGE_GEN)
+# Create local VHDL BOOTROM image
+bl_image: main.bin $(IMAGE_GEN)
 	@set -e
 	@$(IMAGE_GEN) -bld_img $< $(BOOT_VHD) $(shell basename $(CURDIR))
 
-# Install image to VHDL source directory
-install-$(BOOT_VHD): $(BOOT_VHD)
+# Install BOOTROM image to VHDL source directory
+bootloader: bl_image
 	@set -e
 	@echo "Installing bootloader image to $(NEORV32_RTL_PATH)/core/$(BOOT_VHD)"
 	@cp $(BOOT_VHD) $(NEORV32_RTL_PATH)/core/.
 
-# Just an alias
-bl_image: $(BOOT_VHD)
-
-# Compile and install as VHDL bootloader image
-bootloader: bl_image install-$(BOOT_VHD)
-
 # -----------------------------------------------------------------------------
 # Check toolchain
 # -----------------------------------------------------------------------------
@@ -374,26 +364,26 @@ help:
 	@echo "  help         - show this text"
 	@echo "  check        - check toolchain"
 	@echo "  info         - show makefile/toolchain configuration"
-	@echo "  gdb          - run GNU debugging session"
+	@echo "  gdb          - start GNU debugging session"
 	@echo "  asm          - compile and generate <$(APP_ASM)> assembly listing file for manual debugging"
 	@echo "  elf          - compile and generate <$(APP_ELF)> ELF file"
-	@echo "  exe          - compile and generate <$(APP_EXE)> executable image file for upload via default bootloader (binary file)"
-	@echo "  bin          - compile and generate <$(APP_BIN)> RAW executable memory image (binary file)"
-	@echo "  hex          - compile and generate <$(APP_HEX)> RAW executable memory image (hex char file)"
-	@echo "  coe          - compile and generate <$(APP_COE)> RAW executable memory image (COE file)"
-	@echo "  mem          - compile and generate <$(APP_MEM)> RAW executable memory image (MEM file)"
-	@echo "  mif          - compile and generate <$(APP_MIF)> RAW executable memory image (MIF file)"
-	@echo "  image        - compile and generate VHDL IMEM boot image (for application, no header) in local folder"
-	@echo "  install      - compile, generate and install VHDL IMEM boot image (for application, no header)"
+	@echo "  exe          - compile and generate <$(APP_EXE)> executable image file for bootloader upload (includes a HEADER!)"
+	@echo "  bin          - compile and generate <$(APP_BIN)> executable memory image"
+	@echo "  hex          - compile and generate <$(APP_HEX)> executable memory image"
+	@echo "  coe          - compile and generate <$(APP_COE)> executable memory image"
+	@echo "  mem          - compile and generate <$(APP_MEM)> executable memory image"
+	@echo "  mif          - compile and generate <$(APP_MIF)> executable memory image"
+	@echo "  image        - compile and generate VHDL IMEM application boot image <$(APP_VHD)> in local folder"
+	@echo "  install      - compile, generate and install VHDL IMEM application boot image <$(APP_VHD)>"
 	@echo "  sim          - in-console simulation using default/simple testbench and GHDL"
 	@echo "  hdl_lists    - regenerate HDL file-lists (*.f) in NEORV32_HOME/rtl"
 	@echo "  all          - exe + install + hex + bin + asm"
 	@echo "  elf_info     - show ELF layout info"
 	@echo "  elf_sections - show ELF sections"
 	@echo "  clean        - clean up project home folder"
 	@echo "  clean_all    - clean up whole project, core libraries and image generator"
-	@echo "  bl_image     - compile and generate VHDL BOOTROM boot image (for bootloader only, no header) in local folder"
-	@echo "  bootloader   - compile, generate and install VHDL BOOTROM boot image (for bootloader only, no header)"
+	@echo "  bl_image     - compile and generate VHDL BOOTROM bootloader boot image <$(BOOT_VHD)> in local folder"
+	@echo "  bootloader   - compile, generate and install VHDL BOOTROM bootloader boot image <$(BOOT_VHD)>"
 	@echo ""
 	@echo "Variables:"
 	@echo ""
@@ -403,6 +393,7 @@ help:
 	@echo "  MARCH          - Machine architecture: \"$(MARCH)\""
 	@echo "  MABI           - Machine binary interface: \"$(MABI)\""
 	@echo "  APP_INC        - C include folder(s) [append only]: \"$(APP_INC)\""
+	@echo "  APP_SRC        - C source folder(s) [append only]: \"$(APP_SRC)\""
 	@echo "  ASM_INC        - ASM include folder(s) [append only]: \"$(ASM_INC)\""
 	@echo "  RISCV_PREFIX   - Toolchain prefix: \"$(RISCV_PREFIX)\""
 	@echo "  NEORV32_HOME   - NEORV32 home folder: \"$(NEORV32_HOME)\""

sw/common/neorv32.ld

@@ -8,11 +8,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause                                            */
 /* ================================================================================ */
 
-/* Copyright (C) 2014-2020 Free Software Foundation, Inc.
- * Copying and distribution of this script, with or without modification,
- * are permitted in any medium without royalty provided the copyright
- * notice and this notice are preserved. */
-
 OUTPUT_FORMAT("elf32-littleriscv")
 OUTPUT_ARCH(riscv)
 ENTRY(_start)
@@ -24,7 +19,7 @@ SEARCH_DIR("=/usr/lib")
 
 /* ************************************************************************************************* */
 /* +++ NEORV32 memory layout configuration +++                                                       */
-/* If the symbols are not explicitly defined the default configurations are used.                    */
+/* If the "__neorv32_*" symbols are not explicitly defined the default configurations are used.      */
 /* NOTE: section sizes have to be a multiple of 4 bytes; base addresses have to be 32-bit-aligned.   */
 /* ************************************************************************************************* */
 
@@ -41,16 +36,12 @@ __neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x800000
 
 
 /* ************************************************************************************************* */
-/* When compiling the bootloader the ROM section is automatically re-mapped to the                   */
-/* processor-internal bootloader ROM address space.                                                  */
+/* Main memory segments that are relevant for the executable.                                        */
 /* ************************************************************************************************* */
 MEMORY
 {
-  rom  (rx) : ORIGIN = DEFINED(MAKE_BOOTLOADER) ? 0xFFFFC000 : __neorv32_rom_base, LENGTH = DEFINED(MAKE_BOOTLOADER) ? 8K : __neorv32_rom_size
-  ram (rwx) : ORIGIN = __neorv32_ram_base, LENGTH = DEFINED(MAKE_BOOTLOADER) ? 512 : __neorv32_ram_size
-  xip  (rx) : ORIGIN = 0xE0000000, LENGTH = 256M
-  boot (rx) : ORIGIN = 0xFFFFC000, LENGTH = 8K
-  io  (rwx) : ORIGIN = 0xFFFFE000, LENGTH = 8K
+  rom  (rx) : ORIGIN = __neorv32_rom_base, LENGTH = __neorv32_rom_size
+  ram (rwx) : ORIGIN = __neorv32_ram_base, LENGTH = __neorv32_ram_size
 }
 
 

sw/example/eclipse/makefile

@@ -10,9 +10,13 @@ RISCV_PREFIX ?= riscv-none-elf-
 # Override default optimization goal
 EFFORT = -Os
 
-# Add debug symbols for Eclipse
+# Add extended debug symbols for Eclipse
 USER_FLAGS += -ggdb -gdwarf-3
 
+# Additional sources
+APP_SRC += $(wildcard ./*.c)
+APP_INC += -I .
+
 # Adjust processor IMEM size
 USER_FLAGS += -Wl,--defsym,__neorv32_rom_size=16k
 

sw/openocd/openocd_neorv32.cfg

@@ -14,10 +14,10 @@ transport select jtag
 # -------------------------------------------------------------------
 # Target configuration
 # -------------------------------------------------------------------
-set _CHIPNAME neorv32
-jtag newtap $_CHIPNAME cpu -irlen 5
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+set chipname neorv32
+jtag newtap $chipname cpu -irlen 5
+set targetname $chipname.cpu
+target create $targetname.0 riscv -chain-position $targetname
 
 # expose NEORV32-specific CSRs
 riscv expose_csrs 2048=cfureg0