[ppi]: Implement port bulk comparison logic (#2564)

- What I did Implemented port bulk add/remove comparison logic Refactored Port OA to facilitate port config operations - Why I did it To improve switch Fast Boot startup time - How I verified it UT tests VS tests Signed-off-by: Nazarii Hnydyn <[email protected]>
sonic-net · Jul 23, 2023 · d54c767 · d54c767
1 parent a2a5836
commit d54c767
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Showing 18 changed files with 3,045 additions and 956 deletions.
diff --git a/orchagent/Makefile.am b/orchagent/Makefile.am
@@ -4,6 +4,7 @@ INCLUDES = -I $(top_srcdir)/lib \
            -I switch \
            -I flex_counter \
            -I debug_counter \
+           -I port \
            -I pbh \
            -I nhg
 
@@ -58,6 +59,7 @@ orchagent_SOURCES = \
             mplsrouteorch.cpp \
             neighorch.cpp \
             intfsorch.cpp \
+            port/porthlpr.cpp \
             portsorch.cpp \
             fabricportsorch.cpp \
             fgnhgorch.cpp \

diff --git a/orchagent/mirrororch.cpp b/orchagent/mirrororch.cpp
@@ -588,7 +588,7 @@ void MirrorOrch::setSessionState(const string& name, const MirrorEntry& session,
         Port port;
         if ((gMySwitchType == "voq") && (session.type == MIRROR_SESSION_ERSPAN))
         {
-             if (!m_portsOrch->getRecircPort(port, "Rec"))
+             if (!m_portsOrch->getRecircPort(port, Port::Role::Rec))
              {
                  SWSS_LOG_ERROR("Failed to get recirc port for mirror session %s", name.c_str());
                  return;
@@ -946,7 +946,7 @@ bool MirrorOrch::activateSession(const string& name, MirrorEntry& session)
         if (gMySwitchType == "voq")
         {
             Port recirc_port;
-            if (!m_portsOrch->getRecircPort(recirc_port, "Rec"))
+            if (!m_portsOrch->getRecircPort(recirc_port, Port::Role::Rec))
             {
                 SWSS_LOG_ERROR("Failed to get recirc port");
                 return false;
@@ -1177,7 +1177,7 @@ bool MirrorOrch::updateSessionDstPort(const string& name, MirrorEntry& session)
     // Set monitor port to recirc port in voq switch.
     if ((gMySwitchType == "voq") && (session.type == MIRROR_SESSION_ERSPAN))
     {
-         if (!m_portsOrch->getRecircPort(port, "Rec"))
+         if (!m_portsOrch->getRecircPort(port, Port::Role::Rec))
          {
              SWSS_LOG_ERROR("Failed to get recirc port for mirror session %s", name.c_str());
              return false;

diff --git a/orchagent/orch.h b/orchagent/orch.h
@@ -9,8 +9,8 @@
 #include <utility>
 
 extern "C" {
-#include "sai.h"
-#include "saistatus.h"
+#include <sai.h>
+#include <saistatus.h>
 }
 
 #include "dbconnector.h"

diff --git a/orchagent/p4orch/tests/fake_portorch.cpp b/orchagent/p4orch/tests/fake_portorch.cpp
@@ -322,7 +322,7 @@ bool PortsOrch::setVoqInbandIntf(string &alias, string &type)
     return true;
 }
 
-bool PortsOrch::getRecircPort(Port &p, string role)
+bool PortsOrch::getRecircPort(Port &p, Port::Role role)
 {
     return true;
 }
@@ -443,7 +443,7 @@ bool PortsOrch::setHostIntfsStripTag(Port &port, sai_hostif_vlan_tag_t strip)
     return true;
 }
 
-bool PortsOrch::setBridgePortLearnMode(Port &port, string learn_mode)
+bool PortsOrch::setBridgePortLearnMode(Port &port, sai_bridge_port_fdb_learning_mode_t learn_mode)
 {
     return true;
 }
@@ -493,7 +493,7 @@ bool PortsOrch::setDistributionOnLagMember(Port &lagMember, bool enableDistribut
     return true;
 }
 
-bool PortsOrch::addPort(const set<int> &lane_set, uint32_t speed, int an, string fec)
+bool PortsOrch::addPort(const PortConfig &port)
 {
     return true;
 }
@@ -503,7 +503,7 @@ sai_status_t PortsOrch::removePort(sai_object_id_t port_id)
     return SAI_STATUS_SUCCESS;
 }
 
-bool PortsOrch::initPort(const string &alias, const string &role, const int index, const set<int> &lane_set)
+bool PortsOrch::initPort(const PortConfig &port)
 {
     return true;
 }
@@ -527,7 +527,7 @@ bool PortsOrch::setPortMtu(const Port &port, sai_uint32_t mtu)
     return true;
 }
 
-bool PortsOrch::setPortTpid(sai_object_id_t id, sai_uint16_t tpid)
+bool PortsOrch::setPortTpid(Port &port, sai_uint16_t tpid)
 {
     return true;
 }
@@ -542,12 +542,12 @@ bool PortsOrch::getPortPvid(Port &port, sai_uint32_t &pvid)
     return true;
 }
 
-bool PortsOrch::setPortFec(Port &port, std::string &mode)
+bool PortsOrch::setPortFec(Port &port, sai_port_fec_mode_t fec_mode)
 {
     return true;
 }
 
-bool PortsOrch::setPortPfcAsym(Port &port, string pfc_asym)
+bool PortsOrch::setPortPfcAsym(Port &port, sai_port_priority_flow_control_mode_t pfc_asym)
 {
     return true;
 }
@@ -596,7 +596,7 @@ bool PortsOrch::setGearboxPortAttr(const Port &port, dest_port_type_t port_type,
     return true;
 }
 
-task_process_status PortsOrch::setPortAdvSpeeds(sai_object_id_t port_id, std::vector<sai_uint32_t> &speed_list)
+task_process_status PortsOrch::setPortAdvSpeeds(Port &port, std::set<sai_uint32_t> &speed_list)
 {
     return task_success;
 }
@@ -611,22 +611,17 @@ bool PortsOrch::isAutoNegEnabled(sai_object_id_t id)
     return true;
 }
 
-task_process_status PortsOrch::setPortAutoNeg(sai_object_id_t id, int an)
+task_process_status PortsOrch::setPortAutoNeg(Port &port, bool autoneg)
 {
     return task_success;
 }
 
-bool PortsOrch::setPortFecMode(sai_object_id_t id, int fec)
-{
-    return true;
-}
-
-task_process_status PortsOrch::setPortInterfaceType(sai_object_id_t id, sai_port_interface_type_t interface_type)
+task_process_status PortsOrch::setPortInterfaceType(Port &port, sai_port_interface_type_t interface_type)
 {
     return task_success;
 }
 
-task_process_status PortsOrch::setPortAdvInterfaceTypes(sai_object_id_t id, std::vector<uint32_t> &interface_types)
+task_process_status PortsOrch::setPortAdvInterfaceTypes(Port &port, std::set<sai_port_interface_type_t> &interface_types)
 {
     return task_success;
 }
@@ -648,21 +643,6 @@ void PortsOrch::getPortSerdesVal(const std::string &s, std::vector<uint32_t> &la
 {
 }
 
-bool PortsOrch::getPortAdvSpeedsVal(const std::string &s, std::vector<uint32_t> &speed_values)
-{
-    return true;
-}
-
-bool PortsOrch::getPortInterfaceTypeVal(const std::string &s, sai_port_interface_type_t &interface_type)
-{
-    return true;
-}
-
-bool PortsOrch::getPortAdvInterfaceTypesVal(const std::string &s, std::vector<uint32_t> &type_values)
-{
-    return true;
-}
-
 void PortsOrch::removePortSerdesAttribute(sai_object_id_t port_id)
 {
 }

diff --git a/orchagent/port.h b/orchagent/port.h
@@ -2,7 +2,7 @@
 #define SWSS_PORT_H
 
 extern "C" {
-#include "sai.h"
+#include <sai.h>
 }
 
 #include <set>
@@ -12,6 +12,8 @@ extern "C" {
 #include <bitset>
 #include <unordered_set>
 
+#include <macaddress.h>
+
 #define DEFAULT_PORT_VLAN_ID    1
 /*
  * Default MTU is derived from SAI_PORT_ATTR_MTU (1514)
@@ -73,6 +75,9 @@ struct SystemLagInfo
 
 class Port
 {
+public:
+    typedef sai_bridge_port_fdb_learning_mode_t port_learn_mode_t;
+
 public:
     enum Type {
         CPU,
@@ -85,14 +90,21 @@ class Port
         SUBPORT,
         SYSTEM,
         UNKNOWN
-    } ;
+    };
 
-    enum AutoNegMode {
-        AUTONEG_NOT_SET = -1,
-        AUTONEG_OFF = 0,
-        AUTONEG_ON = 1
+    enum Role
+    {
+        Ext, // external
+        Int, // internal
+        Inb, // inband
+        Rec  // recirculation
     };
 
+public:
+    static constexpr std::size_t max_lanes = 8; // Max HW lanes
+    static constexpr std::size_t max_fec_modes = 3; // Max FEC modes (sync with SAI)
+
+public:
     Port() {};
     Port(std::string alias, Type type) :
             m_alias(alias), m_type(type) {};
@@ -114,12 +126,12 @@ class Port
 
     std::string         m_alias;
     Type                m_type = UNKNOWN;
-    int                 m_index = 0;    // PHY_PORT: index
+    uint16_t            m_index = 0;    // PHY_PORT: index
     uint32_t            m_mtu = DEFAULT_MTU;
     uint32_t            m_speed = 0;    // Mbps
-    std::string         m_learn_mode = "hardware";
-    AutoNegMode         m_autoneg = Port::AutoNegMode::AUTONEG_NOT_SET;
-    int                 m_link_training = -1; // -1 means not set, 0 = disabled, 1 = enabled
+    port_learn_mode_t   m_learn_mode = SAI_BRIDGE_PORT_FDB_LEARNING_MODE_HW;
+    bool                m_autoneg = false;
+    bool                m_link_training = false;
     bool                m_admin_state_up = false;
     bool                m_init = false;
     bool                m_l3_vni = false;
@@ -154,9 +166,9 @@ class Port
     uint32_t  m_fdb_count = 0;
     uint32_t  m_up_member_count = 0;
     uint32_t  m_maximum_headroom = 0;
-    std::vector<uint32_t> m_adv_speeds;
+    std::set<uint32_t> m_adv_speeds;
     sai_port_interface_type_t m_interface_type = SAI_PORT_INTERFACE_TYPE_NONE;
-    std::vector<uint32_t> m_adv_interface_types;
+    std::set<sai_port_interface_type_t> m_adv_interface_types;
     bool      m_mpls = false;
     /*
      * Following bit vector is used to lock
@@ -181,8 +193,15 @@ class Port
     /* pre-emphasis */
     std::map<sai_port_serdes_attr_t, std::vector<uint32_t>> m_preemphasis;
 
-    bool m_fec_cfg = false;
-    bool m_an_cfg = false;
+    /* Force initial parameter configuration flags */
+    bool m_an_cfg = false;        // Auto-negotiation (AN)
+    bool m_adv_speed_cfg = false; // Advertised speed
+    bool m_intf_cfg = false;      // Interface type
+    bool m_adv_intf_cfg = false;  // Advertised interface type
+    bool m_fec_cfg = false;       // Forward Error Correction (FEC)
+    bool m_pfc_asym_cfg = false;  // Asymmetric Priority Flow Control (PFC)
+    bool m_lm_cfg = false;        // Forwarding Database (FDB) Learning Mode (LM)
+    bool m_lt_cfg = false;        // Link Training (LT)
 
     int m_cap_an = -1; /* Capability - AutoNeg, -1 means not set */
     int m_cap_lt = -1; /* Capability - LinkTraining, -1 means not set */